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Mon, 10 Feb 2025 05:45:53 -0800 (PST) Message-ID: <7fa3501bd59697e65ab1387e25cb815180c3378c.camel@gmail.com> Subject: Re: [PATCH 02/10] riscv: dts: sophgo: cv18xx: Split into CPU core and peripheral parts From: Alexander Sverdlin To: Krzysztof Kozlowski , soc@lists.linux.dev Cc: Chen Wang , Inochi Amaoto , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Haylen Chu , linux-arm-kernel@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Arnd Bergmann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Date: Mon, 10 Feb 2025 14:45:51 +0100 In-Reply-To: References: <20250209220646.1090868-1-alexander.sverdlin@gmail.com> <20250209220646.1090868-3-alexander.sverdlin@gmail.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.54.2 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Thanks for quick review Krzysztof! On Mon, 2025-02-10 at 09:43 +0100, Krzysztof Kozlowski wrote: > On 09/02/2025 23:06, Alexander Sverdlin wrote: > > Make the peripheral device tree re-usable on ARM64 platform by splittin= g it > > into CPU-core specific and peripheral parts. > >=20 > > Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nuberin= g > > into "plic" interrupt-controller numbering. > >=20 > > Signed-off-by: Alexander Sverdlin > > --- > > =C2=A0 arch/riscv/boot/dts/sophgo/cv181x.dtsi=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 2 +- > > =C2=A0 arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi | 313 ++++++++++++= ++++++ > > =C2=A0 arch/riscv/boot/dts/sophgo/cv18xx.dtsi=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 | 305 +---------------- ^^^^^^^^^^^ [1] > > --- /dev/null > > +++ b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi > > @@ -0,0 +1,313 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > +/* > > + * Copyright (C) 2023 Jisheng Zhang > > + * Copyright (C) 2023 Inochi Amaoto > > + */ > > + > > +#include > > +#include > > +#include > > + > > +/ { > > + osc: oscillator { > > + compatible =3D "fixed-clock"; >=20 > I really doubt that external oscillator is a peripheral. This is either > part of board or the SoC. This is actually a problem of the original cv18xx.dtsi [1]. Do you think I need to fix it as part of my series? This would touch all the pure RiscV boards (using CV18xx SoCs, not SG200x SoCs), which I could avoid otherwise. --=20 Alexander Sverdlin.