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AJvYcCWK7pRvdeMwM08huoOF3/a/28JdiyBTsB9I2IEZwQjYL6IBA4n+8jnRTPUMy0LlmL/IU9K6XUUHBneV4YB4aywrZPnSYqGh+l1zYw== X-Gm-Message-State: AOJu0YyDrpWMmnY+5cs5RtOwEJvA1Pb+F8f8nhWkOHo6oSA6mZuqlq0w OCYsxT3ptIc2sw9Gly877eNQiA21kferJFYUDIeTbHRGgdcv2TAKmM1eou6jCRs= X-Google-Smtp-Source: AGHT+IGE8PKdWdKQ0CmFb3axsD/WyHTpwJ07wSanHT11iLxZDrnuLM5PXMhQIeSftRRiTIbWOUilvw== X-Received: by 2002:a17:907:7701:b0:a6f:a2aa:a4c7 with SMTP id a640c23a62f3a-a79eda04102mr461572866b.3.1721213593565; Wed, 17 Jul 2024 03:53:13 -0700 (PDT) Received: from [192.168.0.3] ([176.61.106.227]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a79bc7f1e5asm431644766b.109.2024.07.17.03.53.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 17 Jul 2024 03:53:13 -0700 (PDT) Message-ID: <7fcc309e-f1c9-4693-a2d1-76df85021dff@linaro.org> Date: Wed, 17 Jul 2024 11:53:11 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/6] clk: qcom: Add camera clock controller driver for SM8150 To: "Satya Priya Kakitapalli (Temp)" , Dmitry Baryshkov Cc: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Abhishek Sahu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephen Boyd , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Ajit Pandey , Imran Shaik , Taniya Das , Jagadeesh Kona References: <20240702-camcc-support-sm8150-v2-0-4baf54ec7333@quicinc.com> <20240702-camcc-support-sm8150-v2-5-4baf54ec7333@quicinc.com> <6124f9e9-3fdf-29b1-128f-c58f5ebe1424@quicinc.com> Content-Language: en-US From: Bryan O'Donoghue In-Reply-To: <6124f9e9-3fdf-29b1-128f-c58f5ebe1424@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 15/07/2024 11:36, Satya Priya Kakitapalli (Temp) wrote: > This clock is PoR ON clock and expected to be always enabled from HW > perspective, we are just re-ensuring it is ON from probe. Modelling this > clock is unnecessary, and we have been following this approach for  gdsc > clock in all the recent chipsets, like for example sm8550 camcc. Having a difficult time following the logic - Re-enabling an already enabled always-on clock is necessary - Modelling the always-on clock in the CCF to park it at XO is unnecessary I think that's a pretty vague argument to be honest. --- bod