From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 552E7C04A6A for ; Tue, 15 Aug 2023 12:32:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234334AbjHOMcD (ORCPT ); Tue, 15 Aug 2023 08:32:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237138AbjHOMbe (ORCPT ); Tue, 15 Aug 2023 08:31:34 -0400 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C656198C for ; Tue, 15 Aug 2023 05:31:31 -0700 (PDT) Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-99bc9e3cbf1so1112551366b.0 for ; Tue, 15 Aug 2023 05:31:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1692102689; x=1692707489; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=E3JquWo+PhnRtxv5g8Z8h2LMAj8f61Bdb2igirOa0jM=; b=dp2t8K3rQLReEkq8+il3zNjCfqzoSV52QkRvqwOJXzNReL1sNVI636pULvQcFPpJaR V+aNLoVRQqZyuXMGW9HVCuVKZXXE54NCrg+DeukyswbIGgkS9zc+S+/e/kxqe6UVRRUl P2aD3nOj1rXv6j+R/JbypnD8E6gOZRDEuYviqyNnGvNpy3B1QpnWNMjCP7SfdEceUvRP WvNYT58K8LtLQhGWIjYzmrcZ/XxgERoOgsaiEwqUg7jv1srkCBgM6KF0Q93pTM/uuS9W 1UNH4iXuKiS+eJXQwDAACduANt1QFGgnYoYgV2izjPWyEBUqsE3JZ3kXzC67yXx67aBO upBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692102689; x=1692707489; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=E3JquWo+PhnRtxv5g8Z8h2LMAj8f61Bdb2igirOa0jM=; b=FzFpCRUpCe2mIvhld3keX4L6lYADr4BN44Up04q77AO0WdGTI6w4JF4sk2aZq2ElnT uIzrMvOmQwD7n7jcSNf/Mb0ZCJ+bN0PuuhsiG9sBhvLTCo82PnTBy2Pw3K4Rj6XcSQmf 5lespmKpTX1uV0+67P/2h8jfX8n27MkMGpLOxd3yOGvQYELa/RrRuadqnyVZCX7MWndu 80t8nWMiVs31Y2nW9d+i8wSClgRa9sDsRhCpvP5WXrT3yv0m7eWPe1kt0G1S8Os3sH3q WhMdvgTmsU60D/bM97/hgabxdQBx/0WM8/bPieEkWqSBNVEEUFCfi59yrWcGg9+MUOuK DqeA== X-Gm-Message-State: AOJu0Yz4wLY0X887cek87PaZjg/LKeYcIXZ6vS5ZAHd/mCO7EXgm4U8v NIIzYPKQ7Z122CNnMiVY9ZMc2Q== X-Google-Smtp-Source: AGHT+IEiYJSPT35S7+7Wzy05+K/JOnc4rIBxfI9zhqdwci8Y3J9mEVZ/8574G6ZEikqQrY/sPJTi9w== X-Received: by 2002:a17:906:7315:b0:98e:4f1:f987 with SMTP id di21-20020a170906731500b0098e04f1f987mr2028420ejc.3.1692102689508; Tue, 15 Aug 2023 05:31:29 -0700 (PDT) Received: from [192.168.1.20] ([178.197.214.188]) by smtp.gmail.com with ESMTPSA id w7-20020aa7da47000000b0052567e6586bsm2349583eds.38.2023.08.15.05.31.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Aug 2023 05:31:29 -0700 (PDT) Message-ID: <7fe554e9-27c3-9af4-8167-ae4329c40eb7@linaro.org> Date: Tue, 15 Aug 2023 14:31:27 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.14.0 Subject: Re: [PATCH v1 2/3] arm64: dts: qcom: sm8450: Add opp table support to PCIe Content-Language: en-US To: Krishna chaitanya chundru , manivannan.sadhasivam@linaro.org Cc: helgaas@kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, quic_parass@quicinc.com, Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" References: <1692102408-7010-1-git-send-email-quic_krichai@quicinc.com> <1692102408-7010-3-git-send-email-quic_krichai@quicinc.com> From: Krzysztof Kozlowski In-Reply-To: <1692102408-7010-3-git-send-email-quic_krichai@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 15/08/2023 14:26, Krishna chaitanya chundru wrote: > PCIe needs to choose the appropriate performance state of RPMH power > domain based upon the PCIe gen speed. This explanation should be also in bindings patch, otherwise why would we consider the bindings patch? > > So, let's add the OPP table support to specify RPMH performance states. > > Signed-off-by: Krishna chaitanya chundru > --- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 47 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 47 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 595533a..681ea9c 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -381,6 +381,49 @@ > }; > }; > > + pcie0_opp_table: opp-table-pcie0 { > + compatible = "operating-points-v2"; > + > + opp-2500000 { > + opp-hz = /bits/ 64 <2500000>; > + opp-level = ; > + }; > + > + opp-5000000 { > + opp-hz = /bits/ 64 <5000000>; > + opp-level = ; > + }; > + > + opp-8000000 { > + opp-hz = /bits/ 64 <8000000>; > + opp-level = ; > + }; > + }; > + > + pcie1_opp_table: opp-table-pcie1 { > + compatible = "operating-points-v2"; > + > + opp-2500000 { > + opp-hz = /bits/ 64 <2500000>; > + opp-level = ; > + }; > + > + opp-5000000 { > + opp-hz = /bits/ 64 <5000000>; > + opp-level = ; > + }; > + > + opp-8000000 { > + opp-hz = /bits/ 64 <8000000>; > + opp-level = ; > + }; > + > + opp-16000000 { > + opp-hz = /bits/ 64 <16000000>; > + opp-level = ; > + }; > + }; > + > reserved_memory: reserved-memory { > #address-cells = <2>; > #size-cells = <2>; > @@ -1803,6 +1846,8 @@ > pinctrl-names = "default"; > pinctrl-0 = <&pcie0_default_state>; > > + operating-points-v2 = <&pcie0_opp_table>; Why the table is not here? Is it shared with multiple devices? Best regards, Krzysztof