From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kevin Hilman Subject: Re: [PATCH v3 2/2] ARM64: dts: meson-axg: enable ethernet for A113D S400 board Date: Fri, 15 Dec 2017 11:31:36 -0800 Message-ID: <7hind7949z.fsf@baylibre.com> References: <20171215021014.231308-1-yixun.lan@amlogic.com> <20171215021014.231308-3-yixun.lan@amlogic.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <20171215021014.231308-3-yixun.lan@amlogic.com> (Yixun Lan's message of "Fri, 15 Dec 2017 10:10:14 +0800") Sender: linux-kernel-owner@vger.kernel.org To: Yixun Lan Cc: devicetree@vger.kernel.org, Neil Armstrong , Jerome Brunet , Giuseppe Cavallaro , Alexandre Torgue , Carlo Caione , linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org List-Id: devicetree@vger.kernel.org Yixun Lan writes: > This is tested in the S400 dev board which use a RTL8211F PHY, > and the pins connect to the 'eth_rgmii_y_pins' group. > > Reviewed-by: Neil Armstrong > Signed-off-by: Yixun Lan > --- > arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts > index 70eca1f8736a..b8c4f1913d28 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts > +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts > @@ -20,3 +20,10 @@ > &uart_AO { > status = "okay"; > }; > + > +ðmac { > + status = "okay"; > + phy-mode = "rgmii"; > + pinctrl-0 = <ð_rgmii_y_pins>; > + pinctrl-names = "default"; > +}; Minor nit: we try to keep these sorted alphabetically. Can you move this above the uart_A0 one? Note: if PATCH 1/1 had applied cleanly, I would have fixed this up myself and not required a respin. Kevin