[PATCH v2] ARM: dts: Add dts file for odroid XU3 board

[PATCH v2] ARM: dts: Add dts file for odroid XU3 board

[Sjoerd Simons]

Add DTS for the Hardkernel Odroid XU3. The name of the DTS file is kept the
same as the vendors naming, which means it's prefixed with exynos5422
instead of exynos5800 as the SoC name even though it includes the
exyno5800 dtsi.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
---
Changes since v1:
  * Add chosen/linux,stdout-path to point the serial console device
  * Change memory start offset to 0x40000000 to match the vendors DTS (pointed
    out by Heesub Shin)
  * Declare base address & size for the memory banks to be used by the MFC

Kevin, Tyler, even though the changes are small i didn't want to just stick
your Tested-By on. Could you both be so kind to retest this on your XU3's ?

Heesub, I would still love to know the reason for having the memory start
address at 0x40000000 for this board?

 arch/arm/boot/dts/Makefile                 |   1 +
 arch/arm/boot/dts/exynos5422-odroidxu3.dts | 332 +++++++++++++++++++++++++++++
 2 files changed, 333 insertions(+)
 create mode 100644 arch/arm/boot/dts/exynos5422-odroidxu3.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 38c89ca..0a898cc 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -86,6 +86,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
 	exynos5420-arndale-octa.dtb \
 	exynos5420-peach-pit.dtb \
 	exynos5420-smdk5420.dtb \
+	exynos5422-odroidxu3.dtb \
 	exynos5440-sd5v1.dtb \
 	exynos5440-ssdk5440.dtb \
 	exynos5800-peach-pi.dtb
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
new file mode 100644
index 0000000..0dc9cf8
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
@@ -0,0 +1,332 @@
+/*
+ * Hardkernel Odroid XU3 board device tree source
+ *
+ * Copyright (c) 2014 Collabora Ltd.
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5800.dtsi"
+
+/ {
+	model = "Hardkernel Odroid XU3";
+	compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", "samsung,exynos5";
+
+	memory {
+		reg = <0x40000000 0x80000000>;
+	};
+
+	chosen {
+		linux,stdout-path = &serial_2;
+	};
+
+	fimd@14400000 {
+		status = "okay";
+	};
+
+	firmware@02073000 {
+		compatible = "samsung,secure-firmware";
+		reg = <0x02073000 0x1000>;
+	};
+
+	fixed-rate-clocks {
+		oscclk {
+			compatible = "samsung,exynos5420-oscclk";
+			clock-frequency = <24000000>;
+		};
+	};
+
+	hsi2c_4: i2c@12CA0000 {
+		status = "okay";
+
+		s2mps11_pmic@66 {
+			compatible = "samsung,s2mps11-pmic";
+			reg = <0x66>;
+			s2mps11,buck2-ramp-delay = <12>;
+			s2mps11,buck34-ramp-delay = <12>;
+			s2mps11,buck16-ramp-delay = <12>;
+			s2mps11,buck6-ramp-enable = <1>;
+			s2mps11,buck2-ramp-enable = <1>;
+			s2mps11,buck3-ramp-enable = <1>;
+			s2mps11,buck4-ramp-enable = <1>;
+
+			s2mps11_osc: clocks {
+				#clock-cells = <1>;
+				clock-output-names = "s2mps11_ap",
+						"s2mps11_cp", "s2mps11_bt";
+			};
+
+			regulators {
+				ldo1_reg: LDO1 {
+					regulator-name = "vdd_ldo1";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+
+				ldo3_reg: LDO3 {
+					regulator-name = "vdd_ldo3";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo5_reg: LDO5 {
+					regulator-name = "vdd_ldo5";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo6_reg: LDO6 {
+					regulator-name = "vdd_ldo6";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+
+				ldo7_reg: LDO7 {
+					regulator-name = "vdd_ldo7";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo8_reg: LDO8 {
+					regulator-name = "vdd_ldo8";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo9_reg: LDO9 {
+					regulator-name = "vdd_ldo9";
+					regulator-min-microvolt = <3000000>;
+					regulator-max-microvolt = <3000000>;
+					regulator-always-on;
+				};
+
+				ldo10_reg: LDO10 {
+					regulator-name = "vdd_ldo10";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo11_reg: LDO11 {
+					regulator-name = "vdd_ldo11";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+
+				ldo12_reg: LDO12 {
+					regulator-name = "vdd_ldo12";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo13_reg: LDO13 {
+					regulator-name = "vdd_ldo13";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+					regulator-always-on;
+				};
+
+				ldo15_reg: LDO15 {
+					regulator-name = "vdd_ldo15";
+					regulator-min-microvolt = <3100000>;
+					regulator-max-microvolt = <3100000>;
+					regulator-always-on;
+				};
+
+				ldo16_reg: LDO16 {
+					regulator-name = "vdd_ldo16";
+					regulator-min-microvolt = <2200000>;
+					regulator-max-microvolt = <2200000>;
+					regulator-always-on;
+				};
+
+				ldo17_reg: LDO17 {
+					regulator-name = "tsp_avdd";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				ldo19_reg: LDO19 {
+					regulator-name = "vdd_sd";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+					regulator-always-on;
+				};
+
+				ldo24_reg: LDO24 {
+					regulator-name = "tsp_io";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+					regulator-always-on;
+				};
+
+				buck1_reg: BUCK1 {
+					regulator-name = "vdd_mif";
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <1300000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				buck2_reg: BUCK2 {
+					regulator-name = "vdd_arm";
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <1500000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				buck3_reg: BUCK3 {
+					regulator-name = "vdd_int";
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <1400000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				buck4_reg: BUCK4 {
+					regulator-name = "vdd_g3d";
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <1400000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				buck5_reg: BUCK5 {
+					regulator-name = "vdd_mem";
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <1400000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				buck6_reg: BUCK6 {
+					regulator-name = "vdd_kfc";
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <1500000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				buck7_reg: BUCK7 {
+					regulator-name = "vdd_1.0v_ldo";
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <1500000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				buck8_reg: BUCK8 {
+					regulator-name = "vdd_1.8v_ldo";
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <1500000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				buck9_reg: BUCK9 {
+					regulator-name = "vdd_2.8v_ldo";
+					regulator-min-microvolt = <3000000>;
+					regulator-max-microvolt = <3750000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				buck10_reg: BUCK10 {
+					regulator-name = "vdd_vmem";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+			};
+		};
+	};
+
+	i2c_2: i2c@12C80000 {
+		samsung,i2c-sda-delay = <100>;
+		samsung,i2c-max-bus-freq = <66000>;
+		status = "okay";
+
+		hdmiddc@50 {
+			compatible = "samsung,exynos4210-hdmiddc";
+			reg = <0x50>;
+		};
+	};
+
+	rtc@101E0000 {
+		status = "okay";
+	};
+};
+
+&hdmi {
+	status = "okay";
+	hpd-gpio = <&gpx3 7 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_hpd_irq>;
+
+	vdd_osc-supply = <&ldo10_reg>;
+	vdd_pll-supply = <&ldo8_reg>;
+	vdd-supply = <&ldo8_reg>;
+};
+
+&mfc {
+	samsung,mfc-r = <0x43000000 0x800000>;
+	samsung,mfc-l = <0x51000000 0x800000>;
+};
+
+&mmc_0 {
+	status = "okay";
+	broken-cd;
+	card-detect-delay = <200>;
+	samsung,dw-mshc-ciu-div = <3>;
+	samsung,dw-mshc-sdr-timing = <0 4>;
+	samsung,dw-mshc-ddr-timing = <0 2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+	bus-width = <8>;
+	cap-mmc-highspeed;
+};
+
+&mmc_2 {
+	status = "okay";
+	card-detect-delay = <200>;
+	samsung,dw-mshc-ciu-div = <3>;
+	samsung,dw-mshc-sdr-timing = <0 4>;
+	samsung,dw-mshc-ddr-timing = <0 2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+	bus-width = <4>;
+	cap-sd-highspeed;
+};
+
+&pinctrl_0 {
+	hdmi_hpd_irq: hdmi-hpd-irq {
+		samsung,pins = "gpx3-7";
+		samsung,pin-function = <0>;
+		samsung,pin-pud = <1>;
+		samsung,pin-drv = <0>;
+	};
+};
+
+&usbdrd_dwc3_0 {
+	dr_mode = "host";
+};
+
+&usbdrd_dwc3_1 {
+	dr_mode = "otg";
+};
-- 
2.1.3

Re: [PATCH v2] ARM: dts: Add dts file for odroid XU3 board

[Tyler Baker]

On 4 December 2014 at 11:27, Sjoerd Simons
<sjoerd.simons@collabora.co.uk> wrote:
> Add DTS for the Hardkernel Odroid XU3. The name of the DTS file is kept the
> same as the vendors naming, which means it's prefixed with exynos5422
> instead of exynos5800 as the SoC name even though it includes the
> exyno5800 dtsi.
>
> Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>

Tested-by: Tyler Baker <tyler.baker@linaro.org>

Tested this atop of next-20141204, both on exynos_defconfig and
multi_v7_defconfig. All configurations boot fine on my odroid-xu3
board.

Cheers,
Tyler

Re: [PATCH v2] ARM: dts: Add dts file for odroid XU3 board

[Kevin Hilman]

Sjoerd Simons <sjoerd.simons@collabora.co.uk> writes:

> Add DTS for the Hardkernel Odroid XU3. The name of the DTS file is kept the
> same as the vendors naming, which means it's prefixed with exynos5422
> instead of exynos5800 as the SoC name even though it includes the
> exyno5800 dtsi.
>
> Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
> ---
> Changes since v1:
>   * Add chosen/linux,stdout-path to point the serial console device
>   * Change memory start offset to 0x40000000 to match the vendors DTS (pointed
>     out by Heesub Shin)
>   * Declare base address & size for the memory banks to be used by the MFC
>
> Kevin, Tyler, even though the changes are small i didn't want to just stick
> your Tested-By on. Could you both be so kind to retest this on your XU3's ?

Tested-by: Kevin Hilman <khilman@linaro.org>

Tested on top of linux-next(ish) and Javier's dp-integ branch and it's
booting fine including HDMI display output.

Kevin

Re: [PATCH v2] ARM: dts: Add dts file for odroid XU3 board

[Joonyoung Shim]

Hi Sjoerd,

On 12/05/2014 04:27 AM, Sjoerd Simons wrote:
> Add DTS for the Hardkernel Odroid XU3. The name of the DTS file is kept the
> same as the vendors naming, which means it's prefixed with exynos5422
> instead of exynos5800 as the SoC name even though it includes the
> exyno5800 dtsi.
> 
> Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
> ---
> Changes since v1:
>   * Add chosen/linux,stdout-path to point the serial console device
>   * Change memory start offset to 0x40000000 to match the vendors DTS (pointed
>     out by Heesub Shin)
>   * Declare base address & size for the memory banks to be used by the MFC
> 
> Kevin, Tyler, even though the changes are small i didn't want to just stick
> your Tested-By on. Could you both be so kind to retest this on your XU3's ?
> 
> Heesub, I would still love to know the reason for having the memory start
> address at 0x40000000 for this board?
> 
>  arch/arm/boot/dts/Makefile                 |   1 +
>  arch/arm/boot/dts/exynos5422-odroidxu3.dts | 332 +++++++++++++++++++++++++++++
>  2 files changed, 333 insertions(+)
>  create mode 100644 arch/arm/boot/dts/exynos5422-odroidxu3.dts
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 38c89ca..0a898cc 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -86,6 +86,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
>  	exynos5420-arndale-octa.dtb \
>  	exynos5420-peach-pit.dtb \
>  	exynos5420-smdk5420.dtb \
> +	exynos5422-odroidxu3.dtb \
>  	exynos5440-sd5v1.dtb \
>  	exynos5440-ssdk5440.dtb \
>  	exynos5800-peach-pi.dtb
> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
> new file mode 100644
> index 0000000..0dc9cf8
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
> @@ -0,0 +1,332 @@
> +/*
> + * Hardkernel Odroid XU3 board device tree source
> + *
> + * Copyright (c) 2014 Collabora Ltd.
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
> + *		http://www.samsung.com
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +/dts-v1/;
> +#include "exynos5800.dtsi"
> +
> +/ {
> +	model = "Hardkernel Odroid XU3";
> +	compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", "samsung,exynos5";
> +
> +	memory {
> +		reg = <0x40000000 0x80000000>;
> +	};
> +
> +	chosen {
> +		linux,stdout-path = &serial_2;
> +	};
> +
> +	fimd@14400000 {
> +		status = "okay";
> +	};
> +
> +	firmware@02073000 {
> +		compatible = "samsung,secure-firmware";
> +		reg = <0x02073000 0x1000>;
> +	};
> +
> +	fixed-rate-clocks {
> +		oscclk {
> +			compatible = "samsung,exynos5420-oscclk";
> +			clock-frequency = <24000000>;
> +		};
> +	};
> +
> +	hsi2c_4: i2c@12CA0000 {
> +		status = "okay";
> +
> +		s2mps11_pmic@66 {
> +			compatible = "samsung,s2mps11-pmic";
> +			reg = <0x66>;
> +			s2mps11,buck2-ramp-delay = <12>;
> +			s2mps11,buck34-ramp-delay = <12>;
> +			s2mps11,buck16-ramp-delay = <12>;
> +			s2mps11,buck6-ramp-enable = <1>;
> +			s2mps11,buck2-ramp-enable = <1>;
> +			s2mps11,buck3-ramp-enable = <1>;
> +			s2mps11,buck4-ramp-enable = <1>;
> +
> +			s2mps11_osc: clocks {
> +				#clock-cells = <1>;
> +				clock-output-names = "s2mps11_ap",
> +						"s2mps11_cp", "s2mps11_bt";
> +			};
> +
> +			regulators {
> +				ldo1_reg: LDO1 {
> +					regulator-name = "vdd_ldo1";
> +					regulator-min-microvolt = <1000000>;
> +					regulator-max-microvolt = <1000000>;
> +					regulator-always-on;
> +				};
> +
> +				ldo3_reg: LDO3 {
> +					regulator-name = "vdd_ldo3";
> +					regulator-min-microvolt = <1800000>;
> +					regulator-max-microvolt = <1800000>;
> +					regulator-always-on;
> +				};
> +
> +				ldo5_reg: LDO5 {
> +					regulator-name = "vdd_ldo5";
> +					regulator-min-microvolt = <1800000>;
> +					regulator-max-microvolt = <1800000>;
> +					regulator-always-on;
> +				};
> +
> +				ldo6_reg: LDO6 {
> +					regulator-name = "vdd_ldo6";
> +					regulator-min-microvolt = <1000000>;
> +					regulator-max-microvolt = <1000000>;
> +					regulator-always-on;
> +				};
> +
> +				ldo7_reg: LDO7 {
> +					regulator-name = "vdd_ldo7";
> +					regulator-min-microvolt = <1800000>;
> +					regulator-max-microvolt = <1800000>;
> +					regulator-always-on;
> +				};
> +
> +				ldo8_reg: LDO8 {
> +					regulator-name = "vdd_ldo8";
> +					regulator-min-microvolt = <1800000>;
> +					regulator-max-microvolt = <1800000>;
> +					regulator-always-on;
> +				};
> +
> +				ldo9_reg: LDO9 {
> +					regulator-name = "vdd_ldo9";
> +					regulator-min-microvolt = <3000000>;
> +					regulator-max-microvolt = <3000000>;
> +					regulator-always-on;
> +				};
> +
> +				ldo10_reg: LDO10 {
> +					regulator-name = "vdd_ldo10";
> +					regulator-min-microvolt = <1800000>;
> +					regulator-max-microvolt = <1800000>;
> +					regulator-always-on;
> +				};
> +
> +				ldo11_reg: LDO11 {
> +					regulator-name = "vdd_ldo11";
> +					regulator-min-microvolt = <1000000>;
> +					regulator-max-microvolt = <1000000>;
> +					regulator-always-on;
> +				};
> +
> +				ldo12_reg: LDO12 {
> +					regulator-name = "vdd_ldo12";
> +					regulator-min-microvolt = <1800000>;
> +					regulator-max-microvolt = <1800000>;
> +					regulator-always-on;
> +				};
> +
> +				ldo13_reg: LDO13 {
> +					regulator-name = "vdd_ldo13";
> +					regulator-min-microvolt = <2800000>;
> +					regulator-max-microvolt = <2800000>;
> +					regulator-always-on;
> +				};
> +
> +				ldo15_reg: LDO15 {
> +					regulator-name = "vdd_ldo15";
> +					regulator-min-microvolt = <3100000>;
> +					regulator-max-microvolt = <3100000>;
> +					regulator-always-on;
> +				};
> +
> +				ldo16_reg: LDO16 {
> +					regulator-name = "vdd_ldo16";
> +					regulator-min-microvolt = <2200000>;
> +					regulator-max-microvolt = <2200000>;
> +					regulator-always-on;
> +				};
> +
> +				ldo17_reg: LDO17 {
> +					regulator-name = "tsp_avdd";
> +					regulator-min-microvolt = <3300000>;
> +					regulator-max-microvolt = <3300000>;
> +					regulator-always-on;
> +				};
> +
> +				ldo19_reg: LDO19 {
> +					regulator-name = "vdd_sd";
> +					regulator-min-microvolt = <2800000>;
> +					regulator-max-microvolt = <2800000>;
> +					regulator-always-on;
> +				};
> +
> +				ldo24_reg: LDO24 {
> +					regulator-name = "tsp_io";
> +					regulator-min-microvolt = <2800000>;
> +					regulator-max-microvolt = <2800000>;
> +					regulator-always-on;
> +				};
> +
> +				buck1_reg: BUCK1 {
> +					regulator-name = "vdd_mif";
> +					regulator-min-microvolt = <800000>;
> +					regulator-max-microvolt = <1300000>;
> +					regulator-always-on;
> +					regulator-boot-on;
> +				};
> +
> +				buck2_reg: BUCK2 {
> +					regulator-name = "vdd_arm";
> +					regulator-min-microvolt = <800000>;
> +					regulator-max-microvolt = <1500000>;
> +					regulator-always-on;
> +					regulator-boot-on;
> +				};
> +
> +				buck3_reg: BUCK3 {
> +					regulator-name = "vdd_int";
> +					regulator-min-microvolt = <800000>;
> +					regulator-max-microvolt = <1400000>;
> +					regulator-always-on;
> +					regulator-boot-on;
> +				};
> +
> +				buck4_reg: BUCK4 {
> +					regulator-name = "vdd_g3d";
> +					regulator-min-microvolt = <800000>;
> +					regulator-max-microvolt = <1400000>;
> +					regulator-always-on;
> +					regulator-boot-on;
> +				};
> +
> +				buck5_reg: BUCK5 {
> +					regulator-name = "vdd_mem";
> +					regulator-min-microvolt = <800000>;
> +					regulator-max-microvolt = <1400000>;
> +					regulator-always-on;
> +					regulator-boot-on;
> +				};
> +
> +				buck6_reg: BUCK6 {
> +					regulator-name = "vdd_kfc";
> +					regulator-min-microvolt = <800000>;
> +					regulator-max-microvolt = <1500000>;
> +					regulator-always-on;
> +					regulator-boot-on;
> +				};
> +
> +				buck7_reg: BUCK7 {
> +					regulator-name = "vdd_1.0v_ldo";
> +					regulator-min-microvolt = <800000>;
> +					regulator-max-microvolt = <1500000>;
> +					regulator-always-on;
> +					regulator-boot-on;
> +				};
> +
> +				buck8_reg: BUCK8 {
> +					regulator-name = "vdd_1.8v_ldo";
> +					regulator-min-microvolt = <800000>;
> +					regulator-max-microvolt = <1500000>;
> +					regulator-always-on;
> +					regulator-boot-on;
> +				};
> +
> +				buck9_reg: BUCK9 {
> +					regulator-name = "vdd_2.8v_ldo";
> +					regulator-min-microvolt = <3000000>;
> +					regulator-max-microvolt = <3750000>;
> +					regulator-always-on;
> +					regulator-boot-on;
> +				};
> +
> +				buck10_reg: BUCK10 {
> +					regulator-name = "vdd_vmem";
> +					regulator-min-microvolt = <2850000>;
> +					regulator-max-microvolt = <2850000>;
> +					regulator-always-on;
> +					regulator-boot-on;
> +				};
> +			};
> +		};
> +	};
> +
> +	i2c_2: i2c@12C80000 {
> +		samsung,i2c-sda-delay = <100>;
> +		samsung,i2c-max-bus-freq = <66000>;
> +		status = "okay";
> +
> +		hdmiddc@50 {
> +			compatible = "samsung,exynos4210-hdmiddc";
> +			reg = <0x50>;
> +		};
> +	};
> +
> +	rtc@101E0000 {
> +		status = "okay";
> +	};
> +};
> +
> +&hdmi {
> +	status = "okay";
> +	hpd-gpio = <&gpx3 7 0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&hdmi_hpd_irq>;
> +
> +	vdd_osc-supply = <&ldo10_reg>;
> +	vdd_pll-supply = <&ldo8_reg>;
> +	vdd-supply = <&ldo8_reg>;

ldo10 and ldo8 are right? I think ldo7 and ldo6 are related with hdmi
from schematic.

Thanks.

Re: [PATCH v2] ARM: dts: Add dts file for odroid XU3 board

[Sjoerd Simons]

[-- Attachment #1: Type: text/plain, Size: 2062 bytes --]

On Mon, 2015-01-05 at 17:18 +0900, Joonyoung Shim wrote:
> Hi Sjoerd,
> 
> On 12/05/2014 04:27 AM, Sjoerd Simons wrote:
> > Add DTS for the Hardkernel Odroid XU3. The name of the DTS file is kept the
> > same as the vendors naming, which means it's prefixed with exynos5422
> > instead of exynos5800 as the SoC name even though it includes the
> > exyno5800 dtsi.
> > 
> > Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
> > ---
> > Changes since v1:
> >   * Add chosen/linux,stdout-path to point the serial console device
> >   * Change memory start offset to 0x40000000 to match the vendors DTS (pointed
> >     out by Heesub Shin)
> >   * Declare base address & size for the memory banks to be used by the MFC
> > 
> > Kevin, Tyler, even though the changes are small i didn't want to just stick
> > your Tested-By on. Could you both be so kind to retest this on your XU3's ?
> > 
> > Heesub, I would still love to know the reason for having the memory start
> > address at 0x40000000 for this board?
> > 
> >  arch/arm/boot/dts/Makefile                 |   1 +
> >  arch/arm/boot/dts/exynos5422-odroidxu3.dts | 332 +++++++++++++++++++++++++++++
> >  2 files changed, 333 insertions(+)
> >  create mode 100644 arch/arm/boot/dts/exynos5422-odroidxu3.dts
> > 
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index 38c89ca..0a898cc 100644


> > +
> > +&hdmi {
> > +	status = "okay";
> > +	hpd-gpio = <&gpx3 7 0>;
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&hdmi_hpd_irq>;
> > +
> > +	vdd_osc-supply = <&ldo10_reg>;
> > +	vdd_pll-supply = <&ldo8_reg>;
> > +	vdd-supply = <&ldo8_reg>;
> 
> ldo10 and ldo8 are right? I think ldo7 and ldo6 are related with hdmi
> from schematic.

Nice catch. I followed hardkernels dts here, which refers to ldo10 &
ldo8, however double-checking the schematics indeed indicate that ldo7
and ldo6 are used the HDMI supplies. 

I'll do some testing and follow-up

-- 
Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Collabora Ltd.

[-- Attachment #2: smime.p7s --]
[-- Type: application/x-pkcs7-signature, Size: 6170 bytes --]

Re: [PATCH v2] ARM: dts: Add dts file for odroid XU3 board

[Anand Moon]

Hi Sjoerd,

I am using 3.18.0 kernel on my odroidxu3 board.
Using exynos_defconfig I am able to boot the board.

Are you able to get all the 8 core CPU up and running ?


Only 4 core cpu's are on my board. Also CpuFreq is not working.

Can you share some point on this.


root@odroid-xu3:/usr/src/odroidxu3-3.18.y-debug# cat /proc/cpuinfo | grep processor
processor : 0
processor : 5
processor : 6
processor : 7


Below are the logs of the board.

[    9.720905] Registering SWP/SWPB emulation handler
[    9.725457] big.LITTLE switcher initializing
[    9.729518] CPU0 paired with CPU4
[    9.732805] CPU5 paired with CPU3
[    9.736069] CPU6 paired with CPU2
[    9.739386] CPU7 paired with CPU1
[    9.742688] GIC ID for CPU 0 cluster 1 is 4
[    9.746816] GIC ID for CPU 0 cluster 0 is 0
[    9.800575] IRQ153 no longer affine to CPU1
[    9.803065] CPU1: shutdown
[    9.813482] GIC ID for CPU 1 cluster 0 is 1
[    9.869776] IRQ154 no longer affine to CPU2
[    9.872218] CPU2: shutdown
[    9.879985] GIC ID for CPU 2 cluster 0 is 2
[    9.924656] IRQ155 no longer affine to CPU3
[    9.927094] CPU3: shutdown
[    9.935544] GIC ID for CPU 3 cluster 0 is 3
[    9.989578] IRQ160 no longer affine to CPU4
[    9.991787] CPU4: shutdown
[   10.001003] GIC ID for CPU 1 cluster 1 is 5
[   10.003812] GIC ID for CPU 2 cluster 1 is 6
[   10.007976] GIC ID for CPU 3 cluster 1 is 7
[   10.015308] big.LITTLE switcher initialized
[   10.031368] registered taskstats version 1
[   10.038110] pinctrl core: add 2 pinmux maps
[   10.038374] samsung-pinctrl 13400000.pinctrl: found group selector 39 for gpx3-7
[   10.038541] samsung-pinctrl 13400000.pinctrl: found group selector 39 for gpx3-7
[   10.038586] samsung-pinctrl 13400000.pinctrl: request pin 39 (gpx3-7) for 14530000.hdmi
[   10.039440] of_get_named_gpiod_flags: parsed 'hpd-gpio' property of node '/hdmi@14530000[0]' - status (0)
[   10.040227] exynos-hdmi 14530000.hdmi: Looking up vdd-supply from device tree
[   10.042869] exynos-hdmi 14530000.hdmi: Looking up vdd_osc-supply from device tree
[   10.044700] exynos-hdmi 14530000.hdmi: Looking up vdd_pll-supply from device tree
[   10.046528] exynos-hdmi 14530000.hdmi: Looking up hdmi-en-supply from device tree
[   10.046558] exynos-hdmi 14530000.hdmi: Looking up hdmi-en-supply property in node /hdmi@14530000 failed
[   10.048281] samsung-pinctrl 13400000.pinctrl: request pin 39 (gpx3-7) for gpx3:39
[   10.071915] exynos-mixer 14450000.mixer: probe start
[   10.076942] exynos-sysmmu 14650000.sysmmu: Enabled
[   10.076975] exynos-mixer 14450000.mixer: exynos_iommu_attach_device: Attached IOMMU with pgtable 0x42264000
[   10.077570] exynos-drm exynos-drm: bound 14450000.mixer (ops mixer_component_ops)
[   10.089655] exynos-drm exynos-drm: bound 14530000.hdmi (ops hdmi_component_ops)
[   10.095639] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[   10.102242] [drm] No driver support for vblank timestamp query.
[   10.161814] cma: cma_alloc(cma c11c3218, count 2025, align 8)
[   10.256074] cma: cma_alloc(): returned ef6cd400
[   10.457934] Console: switching to colour frame buffer device 274x77
[   10.511095] exynos-drm exynos-drm: fb0:  frame buffer device
[   10.516212] exynos-drm exynos-drm: registered panic notifier
[   10.537871] [drm] Initialized exynos 1.0.0 20110530 on minor 0
[   10.545873] s3c-rtc 101e0000.rtc: setting system clock to 2015-01-07 17:50:09 UTC (1420653009)
[   10.553979] power-domain: Power-off latency exceeded, new value 388375 ns
[   10.560076] power-domain: Power-off latency exceeded, new value 6221750 ns
[   10.567225] power-domain: Power-off latency exceeded, new value 248791 ns
[   10.573666] power-domain: Power-off latency exceeded, new value 6502916 ns
[   11.093083] MAIN_DC: disabling
[   11.099738] ALSA device list:
[   11.101347]   No soundcards found.
[   11.117975] Freeing unused kernel memory: 1732K (c079b000 - c094c000)
[   11.775702] systemd-udevd[1676]: starting version 204
[   15.298783] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
[   17.878286] init: plymouth-upstart-bridge main process (1732) terminated with status 1
[   17.885458] init: plymouth-upstart-bridge main process ended, respawning
[   18.211733] init: plymouth-upstart-bridge main process (1741) terminated with status 1
[   18.219007] init: plymouth-upstart-bridge main process ended, respawning
[   18.432104] init: plymouth-upstart-bridge main process (1745) terminated with status 1
[   18.439365] init: plymouth-upstart-bridge main process ended, respawning
[   22.612268] EXT4-fs (mmcblk0p2): re-mounted. Opts: errors=remount-ro
[   26.072597] systemd-udevd[1923]: starting version 204
[   32.854190] Bluetooth: Core ver 2.19
[   32.856710] NET: Registered protocol family 31
[   32.856733] Bluetooth: HCI device and connection manager initialized
[   32.857604] Bluetooth: HCI socket layer initialized
[   32.877598] Bluetooth: L2CAP socket layer initialized
[   32.879515] Bluetooth: SCO socket layer initialized
[   33.282331] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[   33.282356] Bluetooth: BNEP filters: protocol multicast
[   33.282600] Bluetooth: BNEP socket layer initialized
[   33.371899] _cpu_up: attempt to bring up CPU 2 failed
[   33.380836] Bluetooth: RFCOMM TTY layer initialized
[   33.381088] Bluetooth: RFCOMM socket layer initialized
[   33.381439] Bluetooth: RFCOMM ver 1.11
[   33.410276] _cpu_up: attempt to bring up CPU 3 failed
[   33.414848] _cpu_up: attempt to bring up CPU 4 failed
[   33.419857] _cpu_up: attempt to bring up CPU 1 failed
[   38.518916] NET: Registered protocol family 10
[   46.590494] init: failsafe main process (2550) killed by TERM signal
[   50.596528] smsc95xx 5-1.1:1.0 eth0: hardware isn't capable of remote wakeup


-Anand Moon



On Monday, January 5, 2015 9:00 PM, Sjoerd Simons <sjoerd.simons@collabora.co.uk> wrote:
On Mon, 2015-01-05 at 17:18 +0900, Joonyoung Shim wrote:
> Hi Sjoerd,
> 
> On 12/05/2014 04:27 AM, Sjoerd Simons wrote:
> > Add DTS for the Hardkernel Odroid XU3. The name of the DTS file is kept the
> > same as the vendors naming, which means it's prefixed with exynos5422
> > instead of exynos5800 as the SoC name even though it includes the
> > exyno5800 dtsi.
> > 
> > Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
> > ---
> > Changes since v1:
> >   * Add chosen/linux,stdout-path to point the serial console device
> >   * Change memory start offset to 0x40000000 to match the vendors DTS (pointed
> >     out by Heesub Shin)
> >   * Declare base address & size for the memory banks to be used by the MFC
> > 
> > Kevin, Tyler, even though the changes are small i didn't want to just stick
> > your Tested-By on. Could you both be so kind to retest this on your XU3's ?
> > 
> > Heesub, I would still love to know the reason for having the memory start
> > address at 0x40000000 for this board?
> > 
> >  arch/arm/boot/dts/Makefile                 |   1 +
> >  arch/arm/boot/dts/exynos5422-odroidxu3.dts | 332 +++++++++++++++++++++++++++++
> >  2 files changed, 333 insertions(+)
> >  create mode 100644 arch/arm/boot/dts/exynos5422-odroidxu3.dts
> > 
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index 38c89ca..0a898cc 100644


> > +
> > +&hdmi {
> > +    status = "okay";
> > +    hpd-gpio = <&gpx3 7 0>;
> > +    pinctrl-names = "default";
> > +    pinctrl-0 = <&hdmi_hpd_irq>;
> > +
> > +    vdd_osc-supply = <&ldo10_reg>;
> > +    vdd_pll-supply = <&ldo8_reg>;
> > +    vdd-supply = <&ldo8_reg>;
> 
> ldo10 and ldo8 are right? I think ldo7 and ldo6 are related with hdmi
> from schematic.

Nice catch. I followed hardkernels dts here, which refers to ldo10 &
ldo8, however double-checking the schematics indeed indicate that ldo7
and ldo6 are used the HDMI supplies. 

I'll do some testing and follow-up

-- 
Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Collabora Ltd.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v2] ARM: dts: Add dts file for odroid XU3 board

[Sjoerd Simons]

[-- Attachment #1: Type: text/plain, Size: 8579 bytes --]

On Wed, 2015-01-07 at 18:37 +0000, Anand Moon wrote:
> Hi Sjoerd,
> 
> I am using 3.18.0 kernel on my odroidxu3 board.
> Using exynos_defconfig I am able to boot the board.
> 
> Are you able to get all the 8 core CPU up and running ?
> 
> 
> Only 4 core cpu's are on my board. Also CpuFreq is not working.
> 
> Can you share some point on this.

The defconfig is using the bL switcher, which pairs up big and little
cores to make them appear as one core.. So for 8 real cores, you'll get
4 "virtual cores".




> 
> root@odroid-xu3:/usr/src/odroidxu3-3.18.y-debug# cat /proc/cpuinfo | grep processor
> processor : 0
> processor : 5
> processor : 6
> processor : 7
> 
> 
> Below are the logs of the board.
> 
> [    9.720905] Registering SWP/SWPB emulation handler
> [    9.725457] big.LITTLE switcher initializing
> [    9.729518] CPU0 paired with CPU4
> [    9.732805] CPU5 paired with CPU3
> [    9.736069] CPU6 paired with CPU2
> [    9.739386] CPU7 paired with CPU1
> [    9.742688] GIC ID for CPU 0 cluster 1 is 4
> [    9.746816] GIC ID for CPU 0 cluster 0 is 0
> [    9.800575] IRQ153 no longer affine to CPU1
> [    9.803065] CPU1: shutdown
> [    9.813482] GIC ID for CPU 1 cluster 0 is 1
> [    9.869776] IRQ154 no longer affine to CPU2
> [    9.872218] CPU2: shutdown
> [    9.879985] GIC ID for CPU 2 cluster 0 is 2
> [    9.924656] IRQ155 no longer affine to CPU3
> [    9.927094] CPU3: shutdown
> [    9.935544] GIC ID for CPU 3 cluster 0 is 3
> [    9.989578] IRQ160 no longer affine to CPU4
> [    9.991787] CPU4: shutdown
> [   10.001003] GIC ID for CPU 1 cluster 1 is 5
> [   10.003812] GIC ID for CPU 2 cluster 1 is 6
> [   10.007976] GIC ID for CPU 3 cluster 1 is 7
> [   10.015308] big.LITTLE switcher initialized
> [   10.031368] registered taskstats version 1
> [   10.038110] pinctrl core: add 2 pinmux maps
> [   10.038374] samsung-pinctrl 13400000.pinctrl: found group selector 39 for gpx3-7
> [   10.038541] samsung-pinctrl 13400000.pinctrl: found group selector 39 for gpx3-7
> [   10.038586] samsung-pinctrl 13400000.pinctrl: request pin 39 (gpx3-7) for 14530000.hdmi
> [   10.039440] of_get_named_gpiod_flags: parsed 'hpd-gpio' property of node '/hdmi@14530000[0]' - status (0)
> [   10.040227] exynos-hdmi 14530000.hdmi: Looking up vdd-supply from device tree
> [   10.042869] exynos-hdmi 14530000.hdmi: Looking up vdd_osc-supply from device tree
> [   10.044700] exynos-hdmi 14530000.hdmi: Looking up vdd_pll-supply from device tree
> [   10.046528] exynos-hdmi 14530000.hdmi: Looking up hdmi-en-supply from device tree
> [   10.046558] exynos-hdmi 14530000.hdmi: Looking up hdmi-en-supply property in node /hdmi@14530000 failed
> [   10.048281] samsung-pinctrl 13400000.pinctrl: request pin 39 (gpx3-7) for gpx3:39
> [   10.071915] exynos-mixer 14450000.mixer: probe start
> [   10.076942] exynos-sysmmu 14650000.sysmmu: Enabled
> [   10.076975] exynos-mixer 14450000.mixer: exynos_iommu_attach_device: Attached IOMMU with pgtable 0x42264000
> [   10.077570] exynos-drm exynos-drm: bound 14450000.mixer (ops mixer_component_ops)
> [   10.089655] exynos-drm exynos-drm: bound 14530000.hdmi (ops hdmi_component_ops)
> [   10.095639] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
> [   10.102242] [drm] No driver support for vblank timestamp query.
> [   10.161814] cma: cma_alloc(cma c11c3218, count 2025, align 8)
> [   10.256074] cma: cma_alloc(): returned ef6cd400
> [   10.457934] Console: switching to colour frame buffer device 274x77
> [   10.511095] exynos-drm exynos-drm: fb0:  frame buffer device
> [   10.516212] exynos-drm exynos-drm: registered panic notifier
> [   10.537871] [drm] Initialized exynos 1.0.0 20110530 on minor 0
> [   10.545873] s3c-rtc 101e0000.rtc: setting system clock to 2015-01-07 17:50:09 UTC (1420653009)
> [   10.553979] power-domain: Power-off latency exceeded, new value 388375 ns
> [   10.560076] power-domain: Power-off latency exceeded, new value 6221750 ns
> [   10.567225] power-domain: Power-off latency exceeded, new value 248791 ns
> [   10.573666] power-domain: Power-off latency exceeded, new value 6502916 ns
> [   11.093083] MAIN_DC: disabling
> [   11.099738] ALSA device list:
> [   11.101347]   No soundcards found.
> [   11.117975] Freeing unused kernel memory: 1732K (c079b000 - c094c000)
> [   11.775702] systemd-udevd[1676]: starting version 204
> [   15.298783] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
> [   17.878286] init: plymouth-upstart-bridge main process (1732) terminated with status 1
> [   17.885458] init: plymouth-upstart-bridge main process ended, respawning
> [   18.211733] init: plymouth-upstart-bridge main process (1741) terminated with status 1
> [   18.219007] init: plymouth-upstart-bridge main process ended, respawning
> [   18.432104] init: plymouth-upstart-bridge main process (1745) terminated with status 1
> [   18.439365] init: plymouth-upstart-bridge main process ended, respawning
> [   22.612268] EXT4-fs (mmcblk0p2): re-mounted. Opts: errors=remount-ro
> [   26.072597] systemd-udevd[1923]: starting version 204
> [   32.854190] Bluetooth: Core ver 2.19
> [   32.856710] NET: Registered protocol family 31
> [   32.856733] Bluetooth: HCI device and connection manager initialized
> [   32.857604] Bluetooth: HCI socket layer initialized
> [   32.877598] Bluetooth: L2CAP socket layer initialized
> [   32.879515] Bluetooth: SCO socket layer initialized
> [   33.282331] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
> [   33.282356] Bluetooth: BNEP filters: protocol multicast
> [   33.282600] Bluetooth: BNEP socket layer initialized
> [   33.371899] _cpu_up: attempt to bring up CPU 2 failed
> [   33.380836] Bluetooth: RFCOMM TTY layer initialized
> [   33.381088] Bluetooth: RFCOMM socket layer initialized
> [   33.381439] Bluetooth: RFCOMM ver 1.11
> [   33.410276] _cpu_up: attempt to bring up CPU 3 failed
> [   33.414848] _cpu_up: attempt to bring up CPU 4 failed
> [   33.419857] _cpu_up: attempt to bring up CPU 1 failed
> [   38.518916] NET: Registered protocol family 10
> [   46.590494] init: failsafe main process (2550) killed by TERM signal
> [   50.596528] smsc95xx 5-1.1:1.0 eth0: hardware isn't capable of remote wakeup
> 
> 
> -Anand Moon
> 
> 
> 
> On Monday, January 5, 2015 9:00 PM, Sjoerd Simons <sjoerd.simons@collabora.co.uk> wrote:
> On Mon, 2015-01-05 at 17:18 +0900, Joonyoung Shim wrote:
> > Hi Sjoerd,
> > 
> > On 12/05/2014 04:27 AM, Sjoerd Simons wrote:
> > > Add DTS for the Hardkernel Odroid XU3. The name of the DTS file is kept the
> > > same as the vendors naming, which means it's prefixed with exynos5422
> > > instead of exynos5800 as the SoC name even though it includes the
> > > exyno5800 dtsi.
> > > 
> > > Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
> > > ---
> > > Changes since v1:
> > >   * Add chosen/linux,stdout-path to point the serial console device
> > >   * Change memory start offset to 0x40000000 to match the vendors DTS (pointed
> > >     out by Heesub Shin)
> > >   * Declare base address & size for the memory banks to be used by the MFC
> > > 
> > > Kevin, Tyler, even though the changes are small i didn't want to just stick
> > > your Tested-By on. Could you both be so kind to retest this on your XU3's ?
> > > 
> > > Heesub, I would still love to know the reason for having the memory start
> > > address at 0x40000000 for this board?
> > > 
> > >  arch/arm/boot/dts/Makefile                 |   1 +
> > >  arch/arm/boot/dts/exynos5422-odroidxu3.dts | 332 +++++++++++++++++++++++++++++
> > >  2 files changed, 333 insertions(+)
> > >  create mode 100644 arch/arm/boot/dts/exynos5422-odroidxu3.dts
> > > 
> > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > > index 38c89ca..0a898cc 100644
> 
> 
> > > +
> > > +&hdmi {
> > > +    status = "okay";
> > > +    hpd-gpio = <&gpx3 7 0>;
> > > +    pinctrl-names = "default";
> > > +    pinctrl-0 = <&hdmi_hpd_irq>;
> > > +
> > > +    vdd_osc-supply = <&ldo10_reg>;
> > > +    vdd_pll-supply = <&ldo8_reg>;
> > > +    vdd-supply = <&ldo8_reg>;
> > 
> > ldo10 and ldo8 are right? I think ldo7 and ldo6 are related with hdmi
> > from schematic.
> 
> Nice catch. I followed hardkernels dts here, which refers to ldo10 &
> ldo8, however double-checking the schematics indeed indicate that ldo7
> and ldo6 are used the HDMI supplies. 
> 
> I'll do some testing and follow-up
> 



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RE: [PATCH v2] ARM: dts: Add dts file for odroid XU3 board

[Jonathan Stone -SISA]

On On Wed, 2015-01-07 at 18:37 +0000, Sjoerd Simons writes wrote:
>On Wed, 2015-01-07 at 18:37 +0000, Anand Moon wrote:>
[...]

>> Only 4 core cpu's are on my board. Also CpuFreq is not working.
> 
> Can you share some point on this.

>The defconfig is using the bL switcher, which pairs up big and little cores to make them appear as one core.. So for 8 real cores, you'll get
>4 "virtual cores".

That configuration is appropriate for the 5420, which allegedly has a hardware bug in the cache-coherence between the Cortex-A7 block and the Cortex-A15 block.
Newer Exynos 5 SoCs -- 5422/5800, 5620, etc -- don't have that bug. The scheduler should configured to  do HMP on all 8 (or 6) cores.
I don't have a 5410, but I assume it has the same bug as the 5420.

The XU3 kernel supplied by HardKernel shows all 8 cores, and does HMP scheduling across all 8.

I tried v1.0 of the Odroid-XU3 DTB patch, applied to linux-next 20150107.  I'm only seeing 1 core running on my Odroid-XU3.  The USB 3.0 port works (great!) but I'm not getting any HDMI output.  I didn't try DisplayPort.   I'll gladly try v2 of the patch on an XU3; is there a better base to apply the patch to?

Re: [PATCH v2] ARM: dts: Add dts file for odroid XU3 board

[Sjoerd Simons]

[-- Attachment #1: Type: text/plain, Size: 2568 bytes --]

On Wed, 2015-01-07 at 23:49 +0000, Jonathan Stone -SISA wrote:
> 
> On On Wed, 2015-01-07 at 18:37 +0000, Sjoerd Simons writes wrote:
> >On Wed, 2015-01-07 at 18:37 +0000, Anand Moon wrote:>
> [...]
> 
> >> Only 4 core cpu's are on my board. Also CpuFreq is not working.
> > 
> > Can you share some point on this.
> 
> >The defconfig is using the bL switcher, which pairs up big and little cores to make them appear as one core.. So for 8 real cores, you'll get
> >4 "virtual cores".
> 
> That configuration is appropriate for the 5420, which allegedly has a hardware bug in the cache-coherence between the Cortex-A7 block and the Cortex-A15 block.
> Newer Exynos 5 SoCs -- 5422/5800, 5620, etc -- don't have that bug. The scheduler should configured to  do HMP on all 8 (or 6) cores.
> I don't have a 5410, but I assume it has the same bug as the 5420.

Yes the kernel/scheduler could be configured like that, but
exynos_defconfig turns on bL rather then HMP. 

Now it's not unthinkable to add code/dts properties to select the
right/preferred scheduling strategy depending on the board (HMP vs. bL).
But proper HMP scheduling is still a work in progress in mainline and
iirc specifically on the XU3 there are open issue wrt. MCPM and its
secure firmware. I've added Kevin to the CC as he's been working on this
topic so should know the status a lot better then i do.

> The XU3 kernel supplied by HardKernel shows all 8 cores, and does HMP scheduling across all 8.

Yes, that's independant of the dts though as mentioned above. Also there
are still opne issues to booting up all cores on an XU3 afaik. See 
   http://www.spinics.net/lists/linux-samsung-soc/msg39523.html

> I tried v1.0 of the Odroid-XU3 DTB patch, applied to linux-next
> 20150107.  I'm only seeing 1 core running on my Odroid-XU3.  The USB
> 3.0 port works (great!) but I'm not getting any HDMI output. I didn't
> try DisplayPort.   I'll gladly try v2 of the patch on an XU3; is there
> a better base to apply the patch to?

HDMI output is broken on all exynos boards in mainline atm. For exynos
5, see the thread here:
 http://www.spinics.net/lists/linux-samsung-soc/msg40708.html

As far as a i know with the DTS as posted (just posted v3 with a small
improvement), all base functionality that can work on mainline (MMC/SD,
network, USB2, USB3) works. Some less important bits (fan control &
power sensors) are outstanding, but that really shouldn't block the
merge of the DTS.

--
Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Collabora Ltd.

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Re: [PATCH v2] ARM: dts: Add dts file for odroid XU3 board

[Anand Moon]

Hi Sjoerd,

Thanks for all the inputs.
I would like to point out another issue.

I have pulled the changes from "git://git.collabora.co.uk/git/user/javier/linux.git" branch "wip/exynos/dp-integ"


And now Hdmi output to monitor flickers and then black screen.

odroid@odroid-xu3:~$ dmesg | grep hdmi
[    2.442286] hdmi-en: no parameters
[    2.443185] reg-fixed-voltage regulators:regulator@1: hdmi-en supplying 0uV
[   10.199757] samsung-pinctrl 13400000.pinctrl: request pin 39 (gpx3-7) for 14530000.hdmi
[   10.208086] of_get_named_gpiod_flags: parsed 'hpd-gpio' property of node '/hdmi@14530000[0]' - status (0)
[   10.217849] exynos-hdmi 14530000.hdmi: Looking up vdd-supply from device tree
[   10.224403] exynos-hdmi 14530000.hdmi: Failed to get supply 'vdd': -517
[   10.230935] [drm:hdmi_resources_init] *ERROR* failed to get regulators
[   10.237472] [drm:hdmi_probe] *ERROR* hdmi_resources_init failed
[   10.243860] platform 14530000.hdmi: Driver exynos-hdmi requests probe deferral
[   14.290745] samsung-pinctrl 13400000.pinctrl: request pin 39 (gpx3-7) for 14530000.hdmi
[   14.299134] of_get_named_gpiod_flags: parsed 'hpd-gpio' property of node '/hdmi@14530000[0]' - status (0)
[   14.308644] exynos-hdmi 14530000.hdmi: Looking up vdd-supply from device tree
[   14.316894] exynos-hdmi 14530000.hdmi: Looking up vdd_osc-supply from device tree
[   14.324316] exynos-hdmi 14530000.hdmi: Looking up vdd_pll-supply from device tree
[   14.331728] exynos-hdmi 14530000.hdmi: Looking up hdmi-en-supply from device tree
[   14.337943] exynos-hdmi 14530000.hdmi: Looking up hdmi-en-supply property in node /hdmi@14530000 failed
[   14.399118] exynos-drm exynos-drm: bound 14530000.hdmi (ops hdmi_component_ops)


I am now observing the kernel bug bellow.
----------------------------------------------------------------------------

[  164.155699] init: plymouth-stop pre-start process (3934) terminated with status 1
[  654.961143] ------------[ cut here ]------------
[  654.964305] kernel BUG at drivers/gpu/drm/drm_irq.c:1032!
[  654.969673] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM
[  654.975475] Modules linked in: cpufreq_ondemand cpufreq_conservative cpufreq_userspace cpufreq_powersave ipv6 rfcomm bnep bluetooth
[  654.987267] CPU: 0 PID: 4075 Comm: Xorg Not tainted 3.18.0-armv71 #24
[  654.993678] task: ddbfc300 ti: ddbd6000 task.ti: ddbd6000
[  654.999055] PC is at drm_vblank_put+0xcc/0xe4
[  655.003386] LR is at mixer_wait_for_vblank+0x11c/0x148
[  655.008493] pc : [<c03eb608>]    lr : [<c040ee4c>]    psr: 60030013
[  655.008493] sp : ddbd7ce8  ip : ddbd7d00  fp : ddbd7cfc
[  655.019930] r10: c0710a78  r9 : ddbd7e50  r8 : dda5f680
[  655.025129] r7 : 00000008  r6 : c0bd7aec  r5 : eb958724  r4 : eb958590
[  655.031627] r3 : eb97d680  r2 : 00000000  r1 : 00000000  r0 : c23f9a40
[  655.038127] Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
[  655.045233] Control: 10c5387d  Table: 5b87806a  DAC: 00000015
[  655.050954] Process Xorg (pid: 4075, stack limit = 0xddbd6238)
[  655.056759] Stack: (0xddbd7ce8 to 0xddbd8000)
[  655.061096] 7ce0:                   eb958590 eb958724 ddbd7d34 ddbd7d00 c040ee4c c03eb548
[  655.069242] 7d00: ddbd7e50 00000000 ddbfc300 c006fba0 ddbd7d10 ddbd7d10 eb955f00 c23f9ed0
[  655.077389] 7d20: c23f9a40 dda5f6e4 ddbd7d4c ddbd7d38 c04045a4 c040ed3c dda5f684 c23f9e40
[  655.085535] 7d40: ddbd7d7c ddbd7d50 c0404ddc c040456c c0404dbc dda5f684 c23f9e40 c23f9a40
[  655.093679] 7d60: dda5f680 dda5f680 ddbd7e50 c0710a78 ddbd7d9c ddbd7d80 c03f2c30 c0404dc8
[  655.101824] 7d80: dda5f680 dda5f680 c23f9a40 c23f9a40 ddbd7dbc ddbd7da0 c03f2c94 c03f2bdc
[  655.109971] 7da0: ddbd6008 600f0013 ddbd7dc4 e9b92f5c ddbd7dfc ddbd7dc0 c03f304c c03f2c40
[  655.118116] 7dc0: c06bc8dc c007ae2c e9b92f5c c23f9e40 dda5f6d8 c23f9a40 dda5f680 ddbd7e50
[  655.126260] 7de0: e9b92f5c c23f9e40 dda5f6d8 c23f9a40 ddbd7e24 ddbd7e00 c03f77f0 c03f2fa0
[  655.134407] 7e00: ddbd7e50 c23f9a40 c1450544 000000af e9b92ec0 ddbd7e50 ddbd7efc ddbd7e28
[  655.142553] 7e20: c03e9bcc c03f7728 600f0013 ed401200 00070001 ddab10c0 ddbd7e5c ddbd7e48
[  655.150697] 7e40: c03f771c 00000004 c00464af bed28bbc 0000001a 00000001 00000001 00000004
[  655.158842] 7e60: 00000020 00000018 00000001 00000000 00000000 00000002 00000002 00000002
[  655.166989] 7e80: 00000000 00001000 00000000 00001000 c007c7a4 c033daa8 00000000 ed4efcc0
[  655.175132] 7ea0: c0160204 ddab53c0 ddab53c0 ddbd6018 00070000 c0160258 ddbd6000 2d068000
[  655.183277] 7ec0: edbe6ce8 c0b85c40 ddbd7ef4 ed4efcc0 c0b7ece8 eb86de18 bed28bbc db83b200
[  655.191422] 7ee0: c017d4f4 00000008 ddbd6000 00000000 ddbd7f7c ddbd7f00 c017d270 c03e99e4
[  655.199568] 7f00: c0179b14 eea4d0c0 ddbd7f3c ddab53c0 db83b200 ddab53c0 eb86de18 db83b208
[  655.207713] 7f20: 00000020 00000000 ddbd7f4c ddbd7f38 c0179b14 00000001 c000ee84 b6fc41a8
[  655.215859] 7f40: ddbd7f6c ddbd7f50 c01896ac c00965f4 b6fc41a8 db83b200 00000008 db83b200
[  655.224005] 7f60: c00464af bed28bbc ddbd6000 00000000 ddbd7fa4 ddbd7f80 c017d4f4 c017ce58
[  655.232150] 7f80: b6fc41a8 bed28bbc c00464af 00000036 c000f0e4 ddbd6000 00000000 ddbd7fa8
[  655.240295] 7fa0: c000ee60 c017d4bc b6fc41a8 bed28bbc 00000008 c00464af bed28bbc 0000001a
[  655.248441] 7fc0: b6fc41a8 bed28bbc c00464af 00000036 bed28c24 00000020 b6fa18c4 00000003
[  655.256586] 7fe0: b6d38044 bed28b9c b6d2b80f b6b7fa36 800f0030 00000008 aaaaaaaa aaaaaaaa
[  655.264744] [<c03eb608>] (drm_vblank_put) from [<c040ee4c>] (mixer_wait_for_vblank+0x11c/0x148)
[  655.273403] [<c040ee4c>] (mixer_wait_for_vblank) from [<c04045a4>] (exynos_drm_crtc_complete_scanout+0x44/0x58)
[  655.283452] [<c04045a4>] (exynos_drm_crtc_complete_scanout) from [<c0404ddc>] (exynos_drm_fb_destroy+0x20/0xd4)
[  655.293509] [<c0404ddc>] (exynos_drm_fb_destroy) from [<c03f2c30>] (drm_framebuffer_free+0x60/0x64)
[  655.302518] [<c03f2c30>] (drm_framebuffer_free) from [<c03f2c94>] (drm_framebuffer_unreference+0x60/0x90)
[  655.312050] [<c03f2c94>] (drm_framebuffer_unreference) from [<c03f304c>] (drm_framebuffer_remove+0xb8/0x124)
[  655.321840] [<c03f304c>] (drm_framebuffer_remove) from [<c03f77f0>] (drm_mode_rmfb+0xd4/0xfc)
[  655.330330] [<c03f77f0>] (drm_mode_rmfb) from [<c03e9bcc>] (drm_ioctl+0x1f4/0x51c)
[  655.337872] [<c03e9bcc>] (drm_ioctl) from [<c017d270>] (do_vfs_ioctl+0x424/0x664)
[  655.345322] [<c017d270>] (do_vfs_ioctl) from [<c017d4f4>] (SyS_ioctl+0x44/0x6c)
[  655.352606] [<c017d4f4>] (SyS_ioctl) from [<c000ee60>] (ret_fast_syscall+0x0/0x48)
[  655.360139] Code: e89da830 e1a00003 ebfffc03 e89da830 (e7f001f2)
[  655.366212] ---[ end trace b3ff27e5920c0972 ]---
[  655.370795] BUG: sleeping function called from invalid context at kernel/locking/rwsem.c:41
[  655.379110] in_atomic(): 0, irqs_disabled(): 128, pid: 4075, name: Xorg
[  655.385693] INFO: lockdep is turned off.
[  655.389592] irq event stamp: 0
[  655.392625] hardirqs last  enabled at (0): [<  (null)>]   (null)
[  655.398604] hardirqs last disabled at (0): [<c0029e00>] copy_process.part.50+0x3a8/0x1778
[  655.406750] softirqs last  enabled at (0): [<c0029e00>] copy_process.part.50+0x3a8/0x1778
[  655.414895] softirqs last disabled at (0): [<  (null)>]   (null)
[  655.420881] CPU: 0 PID: 4075 Comm: Xorg Tainted: G      D        3.18.0-armv71 #24
[  655.428429] [<c0017610>] (unwind_backtrace) from [<c0013360>] (show_stack+0x20/0x24)
[  655.436144] [<c0013360>] (show_stack) from [<c06b8240>] (dump_stack+0x8c/0xcc)
[  655.443338] [<c06b8240>] (dump_stack) from [<c0056bd4>] (__might_sleep+0x180/0x248)
[  655.450957] [<c0056bd4>] (__might_sleep) from [<c06bdf2c>] (down_read+0x38/0xe8)
[  655.458323] [<c06bdf2c>] (down_read) from [<c003e28c>] (exit_signals+0x28/0x158)
[  655.465688] [<c003e28c>] (exit_signals) from [<c002e780>] (do_exit+0xb0/0xc2c)
[  655.472877] [<c002e780>] (do_exit) from [<c00135a4>] (die+0x240/0x2fc)
[  655.479374] [<c00135a4>] (die) from [<c0013688>] (arm_notify_die+0x28/0x60)
[  655.486307] [<c0013688>] (arm_notify_die) from [<c0008338>] (do_undefinstr+0xb8/0x214)
[  655.494194] [<c0008338>] (do_undefinstr) from [<c0013fd0>] (__und_svc_finish+0x0/0x30)
[  655.502071] Exception stack(0xddbd7ca0 to 0xddbd7ce8)
[  655.507103] 7ca0: c23f9a40 00000000 00000000 eb97d680 eb958590 eb958724 c0bd7aec 00000008
[  655.515249] 7cc0: dda5f680 ddbd7e50 c0710a78 ddbd7cfc ddbd7d00 ddbd7ce8 c040ee4c c03eb608
[  655.523388] 7ce0: 60030013 ffffffff
[  655.526863] [<c0013fd0>] (__und_svc_finish) from [<c03eb608>] (drm_vblank_put+0xcc/0xe4)
[  655.534923] [<c03eb608>] (drm_vblank_put) from [<c040ee4c>] (mixer_wait_for_vblank+0x11c/0x148)
[  655.543587] [<c040ee4c>] (mixer_wait_for_vblank) from [<c04045a4>] (exynos_drm_crtc_complete_scanout+0x44/0x58)
[  655.553638] [<c04045a4>] (exynos_drm_crtc_complete_scanout) from [<c0404ddc>] (exynos_drm_fb_destroy+0x20/0xd4)
[  655.563693] [<c0404ddc>] (exynos_drm_fb_destroy) from [<c03f2c30>] (drm_framebuffer_free+0x60/0x64)
[  655.572705] [<c03f2c30>] (drm_framebuffer_free) from [<c03f2c94>] (drm_framebuffer_unreference+0x60/0x90)
[  655.582237] [<c03f2c94>] (drm_framebuffer_unreference) from [<c03f304c>] (drm_framebuffer_remove+0xb8/0x124)
[  655.592027] [<c03f304c>] (drm_framebuffer_remove) from [<c03f77f0>] (drm_mode_rmfb+0xd4/0xfc)
[  655.600517] [<c03f77f0>] (drm_mode_rmfb) from [<c03e9bcc>] (drm_ioctl+0x1f4/0x51c)
[  655.608056] [<c03e9bcc>] (drm_ioctl) from [<c017d270>] (do_vfs_ioctl+0x424/0x664)
[  655.615509] [<c017d270>] (do_vfs_ioctl) from [<c017d4f4>] (SyS_ioctl+0x44/0x6c)
[  655.622789] [<c017d4f4>] (SyS_ioctl) from [<c000ee60>] (ret_fast_syscall+0x0/0x48)


----------------------------------------------------------------------------
Also the regulators seems not getting populated in the device tree.

odroid@odroid-xu3:~$ ls /proc/device-tree/ | grep regulators
regulators
odroid@odroid-xu3:~$ ksrc8

-Anand Moon




On Thursday, January 8, 2015 6:14 PM, Sjoerd Simons <sjoerd.simons@collabora.co.uk> wrote:
On Wed, 2015-01-07 at 23:49 +0000, Jonathan Stone -SISA wrote:
> 
> On On Wed, 2015-01-07 at 18:37 +0000, Sjoerd Simons writes wrote:
> >On Wed, 2015-01-07 at 18:37 +0000, Anand Moon wrote:>
> [...]
> 
> >> Only 4 core cpu's are on my board. Also CpuFreq is not working.
> > 
> > Can you share some point on this.
> 
> >The defconfig is using the bL switcher, which pairs up big and little cores to make them appear as one core.. So for 8 real cores, you'll get
> >4 "virtual cores".
> 
> That configuration is appropriate for the 5420, which allegedly has a hardware bug in the cache-coherence between the Cortex-A7 block and the Cortex-A15 block.
> Newer Exynos 5 SoCs -- 5422/5800, 5620, etc -- don't have that bug. The scheduler should configured to  do HMP on all 8 (or 6) cores.
> I don't have a 5410, but I assume it has the same bug as the 5420.

Yes the kernel/scheduler could be configured like that, but
exynos_defconfig turns on bL rather then HMP. 

Now it's not unthinkable to add code/dts properties to select the
right/preferred scheduling strategy depending on the board (HMP vs. bL).
But proper HMP scheduling is still a work in progress in mainline and
iirc specifically on the XU3 there are open issue wrt. MCPM and its
secure firmware. I've added Kevin to the CC as he's been working on this
topic so should know the status a lot better then i do.

> The XU3 kernel supplied by HardKernel shows all 8 cores, and does HMP scheduling across all 8.

Yes, that's independant of the dts though as mentioned above. Also there
are still opne issues to booting up all cores on an XU3 afaik. See 
  http://www.spinics.net/lists/linux-samsung-soc/msg39523.html

> I tried v1.0 of the Odroid-XU3 DTB patch, applied to linux-next
> 20150107.  I'm only seeing 1 core running on my Odroid-XU3.  The USB
> 3.0 port works (great!) but I'm not getting any HDMI output. I didn't
> try DisplayPort.   I'll gladly try v2 of the patch on an XU3; is there
> a better base to apply the patch to?

HDMI output is broken on all exynos boards in mainline atm. For exynos
5, see the thread here:
http://www.spinics.net/lists/linux-samsung-soc/msg40708.html

As far as a i know with the DTS as posted (just posted v3 with a small
improvement), all base functionality that can work on mainline (MMC/SD,
network, USB2, USB3) works. Some less important bits (fan control &
power sensors) are outstanding, but that really shouldn't block the
merge of the DTS.

--
Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Collabora Ltd.
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Re: [PATCH v2] ARM: dts: Add dts file for odroid XU3 board

[Kukjin Kim]

On 01/08/15 17:49, Sjoerd Simons wrote:
> On Wed, 2015-01-07 at 23:49 +0000, Jonathan Stone -SISA wrote:
>>
>> On On Wed, 2015-01-07 at 18:37 +0000, Sjoerd Simons writes wrote:
>>> On Wed, 2015-01-07 at 18:37 +0000, Anand Moon wrote:>
>> [...]
>>
>>>> Only 4 core cpu's are on my board. Also CpuFreq is not working.
>>>
>>> Can you share some point on this.
>>
>>> The defconfig is using the bL switcher, which pairs up big and little cores to make them appear as one core.. So for 8 real cores, you'll get
>>> 4 "virtual cores".
>>
>> That configuration is appropriate for the 5420, which allegedly has a hardware bug in the cache-coherence between the Cortex-A7 block and the Cortex-A15 block.
>> Newer Exynos 5 SoCs -- 5422/5800, 5620, etc -- don't have that bug. The scheduler should configured to  do HMP on all 8 (or 6) cores.
>> I don't have a 5410, but I assume it has the same bug as the 5420.
> 
> Yes the kernel/scheduler could be configured like that, but
> exynos_defconfig turns on bL rather then HMP. 
> 
> Now it's not unthinkable to add code/dts properties to select the
> right/preferred scheduling strategy depending on the board (HMP vs. bL).
> But proper HMP scheduling is still a work in progress in mainline and
> iirc specifically on the XU3 there are open issue wrt. MCPM and its
> secure firmware. I've added Kevin to the CC as he's been working on this
> topic so should know the status a lot better then i do.
> 
>> The XU3 kernel supplied by HardKernel shows all 8 cores, and does HMP scheduling across all 8.
> 
> Yes, that's independant of the dts though as mentioned above. Also there
> are still opne issues to booting up all cores on an XU3 afaik. See 
>    http://www.spinics.net/lists/linux-samsung-soc/msg39523.html
> 
>> I tried v1.0 of the Odroid-XU3 DTB patch, applied to linux-next
>> 20150107.  I'm only seeing 1 core running on my Odroid-XU3.  The USB
>> 3.0 port works (great!) but I'm not getting any HDMI output. I didn't
>> try DisplayPort.   I'll gladly try v2 of the patch on an XU3; is there
>> a better base to apply the patch to?
> 
> HDMI output is broken on all exynos boards in mainline atm. For exynos
> 5, see the thread here:
>  http://www.spinics.net/lists/linux-samsung-soc/msg40708.html
> 
> As far as a i know with the DTS as posted (just posted v3 with a small
> improvement), all base functionality that can work on mainline (MMC/SD,
> network, USB2, USB3) works. Some less important bits (fan control &
> power sensors) are outstanding, but that really shouldn't block the
> merge of the DTS.
> 
Sjoerd, thanks. I'll take your updated patch once you submit version3.

- Kukjin
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Re: [PATCH v2] ARM: dts: Add dts file for odroid XU3 board

[Kevin Hilman]

Sjoerd Simons <sjoerd.simons@collabora.co.uk> writes:

> On Wed, 2015-01-07 at 23:49 +0000, Jonathan Stone -SISA wrote:
>> 
>> On On Wed, 2015-01-07 at 18:37 +0000, Sjoerd Simons writes wrote:
>> >On Wed, 2015-01-07 at 18:37 +0000, Anand Moon wrote:>
>> [...]
>> 
>> >> Only 4 core cpu's are on my board. Also CpuFreq is not working.
>> > 
>> > Can you share some point on this.
>> 
>> >The defconfig is using the bL switcher, which pairs up big and
>> > little cores to make them appear as one core.. So for 8 real
>> > cores, you'll get
>> >4 "virtual cores".
>> 
>> That configuration is appropriate for the 5420, which allegedly has
>> a hardware bug in the cache-coherence between the Cortex-A7 block
>> and the Cortex-A15 block.
>> Newer Exynos 5 SoCs -- 5422/5800, 5620, etc -- don't have that
>> bug. The scheduler should configured to do HMP on all 8 (or 6)
>> cores.
>> I don't have a 5410, but I assume it has the same bug as the 5420.
>
> Yes the kernel/scheduler could be configured like that, but
> exynos_defconfig turns on bL rather then HMP. 
>
> Now it's not unthinkable to add code/dts properties to select the
> right/preferred scheduling strategy depending on the board (HMP vs. bL).
> But proper HMP scheduling is still a work in progress in mainline 

Yes, HMP scheduling is not yet ready for mainline, which is why the
switcher is enabled by default.  If you turn the switcher off, you will
indeed get all 8 cores, but you may get some rather strange and
sub-optimal results with performance since from the scheduler
perspective, it will balance tasks across all 8 CPUs as if they were
identical.

> and iirc specifically on the XU3 there are open issue wrt. MCPM and
> its secure firmware. I've added Kevin to the CC as he's been working
> on this topic so should know the status a lot better then i do.

The broken firmware issues don't affect scheduling directly, but affect
the low-power states that are available to the kernel.  Since the
firwmware doesn't allow proper access to CCI, low-power states that
require MCPM are not available, which, among other things, means the
clusters can not be powered down.

>> The XU3 kernel supplied by HardKernel shows all 8 cores, and does HMP scheduling across all 8.
>
> Yes, that's independant of the dts though as mentioned above. Also there
> are still opne issues to booting up all cores on an XU3 afaik. See 
>    http://www.spinics.net/lists/linux-samsung-soc/msg39523.html

I haven't looked closely at the hardkernel tree to see what HMP
scheduling patches they're using, but it must be something out of tree.

Kevin