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AJvYcCV0+LlBRhTngby7ATqcYlOAQHEZSo0SsGW+0VYFFQEvw6Z7UagvF5t0xU5kM9syElO+qDgaxBcqxXHxjMAdfhowBIt2lItOWcvkZQ== X-Gm-Message-State: AOJu0YzyT3hsPvKxOx1Cl/KKIgmez9FHQ9GavG6MDeJn9f86sdb4vOYC JcrwFHlJhaJBlArl4JJ+5dMWiwML3FJb/Udq+J+9vHfEosYCGPrLUOeYZuSQ+Dw= X-Google-Smtp-Source: AGHT+IFyC/4QrUfmFma/svm6P7ncU0LS1OeE3p4iwwLxVeaF0tQ3vYyuoA8eoICoNDNcv4AhdWdRLw== X-Received: by 2002:a2e:be0f:0:b0:2df:48a:b8d9 with SMTP id z15-20020a2ebe0f000000b002df048ab8d9mr1837667ljq.35.1714128899379; Fri, 26 Apr 2024 03:54:59 -0700 (PDT) Received: from [10.1.1.109] ([80.111.64.44]) by smtp.gmail.com with ESMTPSA id n6-20020a05600c3b8600b0041892e839bcsm30822115wms.33.2024.04.26.03.54.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Apr 2024 03:54:59 -0700 (PDT) Message-ID: <8023ea8c1eab725baf0389fe34b918bb5dd924c8.camel@linaro.org> Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: samsung: google,gs101-pinctrl needs a clock From: =?ISO-8859-1?Q?Andr=E9?= Draszik To: Krzysztof Kozlowski , Sylwester Nawrocki , Alim Akhtar , Linus Walleij , Rob Herring , Conor Dooley , Tomasz Figa , Peter Griffin , semen.protsenko@linaro.org Cc: Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Date: Fri, 26 Apr 2024 11:54:57 +0100 In-Reply-To: <013f2da9-1d91-4b62-b5b7-d603d0c09aef@kernel.org> References: <20240425-samsung-pinctrl-busclock-v1-0-898a200abe68@linaro.org> <20240425-samsung-pinctrl-busclock-v1-1-898a200abe68@linaro.org> <56a32a2d-2f6f-4f7b-8359-6f3062c010e2@kernel.org> <013f2da9-1d91-4b62-b5b7-d603d0c09aef@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.50.3-1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Thu, 2024-04-25 at 20:18 +0200, Krzysztof Kozlowski wrote: > On 25/04/2024 20:15, Krzysztof Kozlowski wrote: > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 properties: > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 compatible: > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 contains: > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 c= onst: google,gs101-pinctrl > > > +=C2=A0=C2=A0=C2=A0 then: > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 required: > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - clocks > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - clock-names > >=20 > > else: > > =C2=A0 properties: > > =C2=A0=C2=A0=C2=A0 clocks: false > > =C2=A0=C2=A0=C2=A0 clock-names: false > >=20 > > but anyway this is all a bit fragile, because pinctrl is not a driver > > and you rely on initcall ordering. >=20 > It is a driver, although initcall ordering is still there. Anyway, it's > the first soc requiring clock for pinctrl If I see it right, E850 has similar gates, and like on gs101 they're curren= tly also all marked as CLK_IGNORE_UNUSED in the e850 clock driver with a commen= t that a driver update is needed. I've added Sam. Cheers, Andre'