* [PATCH v4 1/8] riscv: dts: microchip: remove icicle memory clocks
2022-05-04 20:30 [PATCH v4 0/8] PolarFire SoC dt for 5.19 Conor Dooley
@ 2022-05-04 20:30 ` Conor Dooley
2022-05-04 20:30 ` [PATCH v4 2/8] riscv: dts: microchip: move sysctrlr out of soc bus Conor Dooley
` (6 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2022-05-04 20:30 UTC (permalink / raw)
To: krzk+dt, palmer, robh+dt
Cc: conor.dooley, Cyril.Jean, daire.mcnamara, paul.walmsley, aou,
palmer, arnd, heiko, devicetree, linux-kernel, linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
The clock properties in the icicle kit's memory entries cause dtbs_check
errors:
arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dtb: /: memory@80000000: 'clocks' does not match any of the regexes: 'pinctrl-[0-9]+'
Get rid of the clocks to avoid the errors.
Reported-by: Palmer Dabbelt <palmer@rivosinc.com>
Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
Fixes: 5b28df37d311 ("riscv: dts: microchip: update peripherals in icicle kit device tree")
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index 3392153dd0f1..c71d6aa6137a 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -32,14 +32,12 @@ cpus {
ddrc_cache_lo: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x2e000000>;
- clocks = <&clkcfg CLK_DDRC>;
status = "okay";
};
ddrc_cache_hi: memory@1000000000 {
device_type = "memory";
reg = <0x10 0x0 0x0 0x40000000>;
- clocks = <&clkcfg CLK_DDRC>;
status = "okay";
};
};
--
2.36.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v4 2/8] riscv: dts: microchip: move sysctrlr out of soc bus
2022-05-04 20:30 [PATCH v4 0/8] PolarFire SoC dt for 5.19 Conor Dooley
2022-05-04 20:30 ` [PATCH v4 1/8] riscv: dts: microchip: remove icicle memory clocks Conor Dooley
@ 2022-05-04 20:30 ` Conor Dooley
2022-05-09 11:04 ` Heiko Stübner
2022-05-04 20:30 ` [PATCH v4 3/8] riscv: dts: microchip: remove soc vendor from filenames Conor Dooley
` (5 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: Conor Dooley @ 2022-05-04 20:30 UTC (permalink / raw)
To: krzk+dt, palmer, robh+dt
Cc: conor.dooley, Cyril.Jean, daire.mcnamara, paul.walmsley, aou,
palmer, arnd, heiko, devicetree, linux-kernel, linux-riscv,
Rob Herring
From: Conor Dooley <conor.dooley@microchip.com>
The MPFS system controller has no registers of its own, so move it out
of the soc node to avoid dtbs_check warnings:
arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dtb: soc: syscontroller: {'compatible': ['microchip,mpfs-sys-controller'], 'mboxes': [[15, 0]], 'status': ['okay']} should not be valid under {'type': 'object'}
Reported-by: Palmer Dabbelt <palmer@rivosinc.com>
Suggested-by: Rob Herring <robh@kernel.org>
Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 746c4d4e7686..bf21a2edd180 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -146,6 +146,11 @@ refclk: mssrefclk {
#clock-cells = <0>;
};
+ syscontroller: syscontroller {
+ compatible = "microchip,mpfs-sys-controller";
+ mboxes = <&mbox 0>;
+ };
+
soc {
#address-cells = <2>;
#size-cells = <2>;
@@ -446,10 +451,5 @@ mbox: mailbox@37020000 {
#mbox-cells = <1>;
status = "disabled";
};
-
- syscontroller: syscontroller {
- compatible = "microchip,mpfs-sys-controller";
- mboxes = <&mbox 0>;
- };
};
};
--
2.36.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v4 2/8] riscv: dts: microchip: move sysctrlr out of soc bus
2022-05-04 20:30 ` [PATCH v4 2/8] riscv: dts: microchip: move sysctrlr out of soc bus Conor Dooley
@ 2022-05-09 11:04 ` Heiko Stübner
0 siblings, 0 replies; 14+ messages in thread
From: Heiko Stübner @ 2022-05-09 11:04 UTC (permalink / raw)
To: krzk+dt, palmer, robh+dt, Conor Dooley
Cc: conor.dooley, Cyril.Jean, daire.mcnamara, paul.walmsley, aou,
palmer, arnd, devicetree, linux-kernel, linux-riscv, Rob Herring
Am Mittwoch, 4. Mai 2022, 22:30:46 CEST schrieb Conor Dooley:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The MPFS system controller has no registers of its own, so move it out
> of the soc node to avoid dtbs_check warnings:
> arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dtb: soc: syscontroller: {'compatible': ['microchip,mpfs-sys-controller'], 'mboxes': [[15, 0]], 'status': ['okay']} should not be valid under {'type': 'object'}
>
> Reported-by: Palmer Dabbelt <palmer@rivosinc.com>
> Suggested-by: Rob Herring <robh@kernel.org>
> Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree")
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> ---
> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> index 746c4d4e7686..bf21a2edd180 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> @@ -146,6 +146,11 @@ refclk: mssrefclk {
> #clock-cells = <0>;
> };
>
> + syscontroller: syscontroller {
> + compatible = "microchip,mpfs-sys-controller";
> + mboxes = <&mbox 0>;
> + };
> +
> soc {
> #address-cells = <2>;
> #size-cells = <2>;
> @@ -446,10 +451,5 @@ mbox: mailbox@37020000 {
> #mbox-cells = <1>;
> status = "disabled";
> };
> -
> - syscontroller: syscontroller {
> - compatible = "microchip,mpfs-sys-controller";
> - mboxes = <&mbox 0>;
> - };
> };
> };
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v4 3/8] riscv: dts: microchip: remove soc vendor from filenames
2022-05-04 20:30 [PATCH v4 0/8] PolarFire SoC dt for 5.19 Conor Dooley
2022-05-04 20:30 ` [PATCH v4 1/8] riscv: dts: microchip: remove icicle memory clocks Conor Dooley
2022-05-04 20:30 ` [PATCH v4 2/8] riscv: dts: microchip: move sysctrlr out of soc bus Conor Dooley
@ 2022-05-04 20:30 ` Conor Dooley
2022-05-04 20:30 ` [PATCH v4 4/8] dt-bindings: riscv: microchip: document icicle reference design Conor Dooley
` (4 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2022-05-04 20:30 UTC (permalink / raw)
To: krzk+dt, palmer, robh+dt
Cc: conor.dooley, Cyril.Jean, daire.mcnamara, paul.walmsley, aou,
palmer, arnd, heiko, devicetree, linux-kernel, linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
Having the SoC vendor both as the directory and in the filename adds
little. Remove microchip from the filenames so that the files will
resemble the other directories in riscv (and arm64). The new names
follow a soc-board.dts & soc{,-fabric}.dtsi pattern.
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/microchip/Makefile | 2 +-
.../microchip/{microchip-mpfs-fabric.dtsi => mpfs-fabric.dtsi} | 0
.../{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} | 2 +-
.../riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} | 2 +-
4 files changed, 3 insertions(+), 3 deletions(-)
rename arch/riscv/boot/dts/microchip/{microchip-mpfs-fabric.dtsi => mpfs-fabric.dtsi} (100%)
rename arch/riscv/boot/dts/microchip/{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} (98%)
rename arch/riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} (99%)
diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
index 855c1502d912..af3a5059b350 100644
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -1,3 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb
+dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi
similarity index 100%
rename from arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
rename to arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
similarity index 98%
rename from arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
rename to arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index c71d6aa6137a..84b0015dfd47 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -3,7 +3,7 @@
/dts-v1/;
-#include "microchip-mpfs.dtsi"
+#include "mpfs.dtsi"
/* Clock frequency (in Hz) of the rtcclk */
#define RTCCLK_FREQ 1000000
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
similarity index 99%
rename from arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
rename to arch/riscv/boot/dts/microchip/mpfs.dtsi
index bf21a2edd180..cc3386068c2d 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -3,7 +3,7 @@
/dts-v1/;
#include "dt-bindings/clock/microchip,mpfs-clock.h"
-#include "microchip-mpfs-fabric.dtsi"
+#include "mpfs-fabric.dtsi"
/ {
#address-cells = <2>;
--
2.36.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v4 4/8] dt-bindings: riscv: microchip: document icicle reference design
2022-05-04 20:30 [PATCH v4 0/8] PolarFire SoC dt for 5.19 Conor Dooley
` (2 preceding siblings ...)
2022-05-04 20:30 ` [PATCH v4 3/8] riscv: dts: microchip: remove soc vendor from filenames Conor Dooley
@ 2022-05-04 20:30 ` Conor Dooley
2022-05-04 20:30 ` [PATCH v4 5/8] riscv: dts: microchip: make the fabric dtsi board specific Conor Dooley
` (3 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2022-05-04 20:30 UTC (permalink / raw)
To: krzk+dt, palmer, robh+dt
Cc: conor.dooley, Cyril.Jean, daire.mcnamara, paul.walmsley, aou,
palmer, arnd, heiko, devicetree, linux-kernel, linux-riscv,
Krzysztof Kozlowski
From: Conor Dooley <conor.dooley@microchip.com>
Add a compatible for the icicle kit's reference design. This represents
the FPGA fabric's contents & is versioned to denote which release of the
reference design it applies to.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bindings/riscv/microchip.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
index 3f981e897126..822a711df9e9 100644
--- a/Documentation/devicetree/bindings/riscv/microchip.yaml
+++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
@@ -20,6 +20,7 @@ properties:
items:
- enum:
- microchip,mpfs-icicle-kit
+ - microchip,mpfs-icicle-reference-rtlv2203
- const: microchip,mpfs
additionalProperties: true
--
2.36.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v4 5/8] riscv: dts: microchip: make the fabric dtsi board specific
2022-05-04 20:30 [PATCH v4 0/8] PolarFire SoC dt for 5.19 Conor Dooley
` (3 preceding siblings ...)
2022-05-04 20:30 ` [PATCH v4 4/8] dt-bindings: riscv: microchip: document icicle reference design Conor Dooley
@ 2022-05-04 20:30 ` Conor Dooley
2022-05-04 20:30 ` [PATCH v4 6/8] dt-bindings: vendor-prefixes: add Sundance DSP Conor Dooley
` (2 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2022-05-04 20:30 UTC (permalink / raw)
To: krzk+dt, palmer, robh+dt
Cc: conor.dooley, Cyril.Jean, daire.mcnamara, paul.walmsley, aou,
palmer, arnd, heiko, devicetree, linux-kernel, linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
Currently mpfs-fabric.dtsi is included by mpfs.dtsi - which is fine
currently since there is only one board with this SoC upstream.
However if another board was added, it would include the fabric contents
of the Icicle Kit's reference design. To avoid this, rename
mpfs-fabric.dtsi to mpfs-icicle-kit-fabric.dtsi & include it in the dts
rather than mpfs.dtsi.
mpfs-icicle-kit-fabric.dtsi specifically matches the 22.03 reference
design for the icicle kit's FPGA fabric & an older version of the
design may not have the i2c or pwm devices - so add the compatible
string to document this.
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../microchip/{mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} | 2 ++
arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 1 +
arch/riscv/boot/dts/microchip/mpfs.dtsi | 1 -
3 files changed, 3 insertions(+), 1 deletion(-)
rename arch/riscv/boot/dts/microchip/{mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} (91%)
diff --git a/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
similarity index 91%
rename from arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi
rename to arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index ccaac3371cf9..0d28858b83f2 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -2,6 +2,8 @@
/* Copyright (c) 2020-2021 Microchip Technology Inc */
/ {
+ compatible = "microchip,mpfs-icicle-reference-rtlv2203", "microchip,mpfs";
+
core_pwm0: pwm@41000000 {
compatible = "microchip,corepwm-rtl-v4";
reg = <0x0 0x41000000 0x0 0xF0>;
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index 84b0015dfd47..739dfa52bed1 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -4,6 +4,7 @@
/dts-v1/;
#include "mpfs.dtsi"
+#include "mpfs-icicle-kit-fabric.dtsi"
/* Clock frequency (in Hz) of the rtcclk */
#define RTCCLK_FREQ 1000000
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index cc3386068c2d..695c4e2807f5 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -3,7 +3,6 @@
/dts-v1/;
#include "dt-bindings/clock/microchip,mpfs-clock.h"
-#include "mpfs-fabric.dtsi"
/ {
#address-cells = <2>;
--
2.36.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v4 6/8] dt-bindings: vendor-prefixes: add Sundance DSP
2022-05-04 20:30 [PATCH v4 0/8] PolarFire SoC dt for 5.19 Conor Dooley
` (4 preceding siblings ...)
2022-05-04 20:30 ` [PATCH v4 5/8] riscv: dts: microchip: make the fabric dtsi board specific Conor Dooley
@ 2022-05-04 20:30 ` Conor Dooley
2022-05-04 20:30 ` [PATCH v4 7/8] dt-bindings: riscv: microchip: add polarberry compatible string Conor Dooley
2022-05-04 20:30 ` [PATCH v4 8/8] riscv: dts: microchip: add the sundance polarberry Conor Dooley
7 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2022-05-04 20:30 UTC (permalink / raw)
To: krzk+dt, palmer, robh+dt
Cc: conor.dooley, Cyril.Jean, daire.mcnamara, paul.walmsley, aou,
palmer, arnd, heiko, devicetree, linux-kernel, linux-riscv,
Krzysztof Kozlowski
From: Conor Dooley <conor.dooley@microchip.com>
Sundance DSP Inc. (https://www.sundancedsp.com/) is a supplier of
high-performance DSP and FPGA processor boards and I/O modules.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 01430973ecec..1d47a38c2a2e 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1197,6 +1197,8 @@ patternProperties:
description: Summit microelectronics
"^sunchip,.*":
description: Shenzhen Sunchip Technology Co., Ltd
+ "^sundance,.*":
+ description: Sundance DSP Inc.
"^sunplus,.*":
description: Sunplus Technology Co., Ltd.
"^SUNW,.*":
--
2.36.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v4 7/8] dt-bindings: riscv: microchip: add polarberry compatible string
2022-05-04 20:30 [PATCH v4 0/8] PolarFire SoC dt for 5.19 Conor Dooley
` (5 preceding siblings ...)
2022-05-04 20:30 ` [PATCH v4 6/8] dt-bindings: vendor-prefixes: add Sundance DSP Conor Dooley
@ 2022-05-04 20:30 ` Conor Dooley
2022-05-04 20:30 ` [PATCH v4 8/8] riscv: dts: microchip: add the sundance polarberry Conor Dooley
7 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2022-05-04 20:30 UTC (permalink / raw)
To: krzk+dt, palmer, robh+dt
Cc: conor.dooley, Cyril.Jean, daire.mcnamara, paul.walmsley, aou,
palmer, arnd, heiko, devicetree, linux-kernel, linux-riscv,
Krzysztof Kozlowski
From: Conor Dooley <conor.dooley@microchip.com>
Add a binding for the Sundance Polarberry board.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bindings/riscv/microchip.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
index 822a711df9e9..1aa7336a9672 100644
--- a/Documentation/devicetree/bindings/riscv/microchip.yaml
+++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
@@ -21,6 +21,7 @@ properties:
- enum:
- microchip,mpfs-icicle-kit
- microchip,mpfs-icicle-reference-rtlv2203
+ - sundance,polarberry
- const: microchip,mpfs
additionalProperties: true
--
2.36.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v4 8/8] riscv: dts: microchip: add the sundance polarberry
2022-05-04 20:30 [PATCH v4 0/8] PolarFire SoC dt for 5.19 Conor Dooley
` (6 preceding siblings ...)
2022-05-04 20:30 ` [PATCH v4 7/8] dt-bindings: riscv: microchip: add polarberry compatible string Conor Dooley
@ 2022-05-04 20:30 ` Conor Dooley
2022-05-09 11:10 ` Heiko Stübner
7 siblings, 1 reply; 14+ messages in thread
From: Conor Dooley @ 2022-05-04 20:30 UTC (permalink / raw)
To: krzk+dt, palmer, robh+dt
Cc: conor.dooley, Cyril.Jean, daire.mcnamara, paul.walmsley, aou,
palmer, arnd, heiko, devicetree, linux-kernel, linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
Add a minimal device tree for the PolarFire SoC based Sundance
PolarBerry.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/microchip/Makefile | 1 +
.../dts/microchip/mpfs-polarberry-fabric.dtsi | 16 +++
.../boot/dts/microchip/mpfs-polarberry.dts | 97 +++++++++++++++++++
3 files changed, 114 insertions(+)
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
index af3a5059b350..39aae7b04f1c 100644
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
+dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
new file mode 100644
index 000000000000..49380c428ec9
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2022 Microchip Technology Inc */
+
+/ {
+ fabric_clk3: fabric-clk3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <62500000>;
+ };
+
+ fabric_clk1: fabric-clk1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+};
diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
new file mode 100644
index 000000000000..1cad5b0d42e1
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2022 Microchip Technology Inc */
+
+/dts-v1/;
+
+#include "mpfs.dtsi"
+#include "mpfs-polarberry-fabric.dtsi"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define MTIMER_FREQ 1000000
+
+/ {
+ model = "Sundance PolarBerry";
+ compatible = "sundance,polarberry", "microchip,mpfs";
+
+ aliases {
+ ethernet0 = &mac1;
+ serial0 = &mmuart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ timebase-frequency = <MTIMER_FREQ>;
+ };
+
+ ddrc_cache_lo: memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x2e000000>;
+ };
+
+ ddrc_cache_hi: memory@1000000000 {
+ device_type = "memory";
+ reg = <0x10 0x00000000 0x0 0xC0000000>;
+ };
+};
+
+/*
+ * phy0 is connected to mac0, but the port itself is on the (optional) carrier
+ * board.
+ */
+&mac0 {
+ status = "disabled";
+ phy-mode = "sgmii";
+ phy-handle = <&phy0>;
+};
+
+&mac1 {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy-handle = <&phy1>;
+ phy1: ethernet-phy@5 {
+ reg = <5>;
+ ti,fifo-depth = <0x01>;
+ };
+ phy0: ethernet-phy@4 {
+ reg = <4>;
+ ti,fifo-depth = <0x01>;
+ };
+};
+
+&mbox {
+ status = "okay";
+};
+
+&mmc {
+ bus-width = <4>;
+ disable-wp;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ card-detect-delay = <200>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&mmuart0 {
+ status = "okay";
+};
+
+&refclk {
+ clock-frequency = <125000000>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&syscontroller {
+ status = "okay";
+};
--
2.36.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v4 8/8] riscv: dts: microchip: add the sundance polarberry
2022-05-04 20:30 ` [PATCH v4 8/8] riscv: dts: microchip: add the sundance polarberry Conor Dooley
@ 2022-05-09 11:10 ` Heiko Stübner
2022-05-09 11:24 ` Conor.Dooley
0 siblings, 1 reply; 14+ messages in thread
From: Heiko Stübner @ 2022-05-09 11:10 UTC (permalink / raw)
To: krzk+dt, palmer, robh+dt, Conor Dooley
Cc: conor.dooley, Cyril.Jean, daire.mcnamara, paul.walmsley, aou,
palmer, arnd, devicetree, linux-kernel, linux-riscv
Am Mittwoch, 4. Mai 2022, 22:30:52 CEST schrieb Conor Dooley:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Add a minimal device tree for the PolarFire SoC based Sundance
> PolarBerry.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> arch/riscv/boot/dts/microchip/Makefile | 1 +
> .../dts/microchip/mpfs-polarberry-fabric.dtsi | 16 +++
> .../boot/dts/microchip/mpfs-polarberry.dts | 97 +++++++++++++++++++
> 3 files changed, 114 insertions(+)
> create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
> create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
>
> diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
> index af3a5059b350..39aae7b04f1c 100644
> --- a/arch/riscv/boot/dts/microchip/Makefile
> +++ b/arch/riscv/boot/dts/microchip/Makefile
> @@ -1,3 +1,4 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
> +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
> obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
> new file mode 100644
> index 000000000000..49380c428ec9
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
> @@ -0,0 +1,16 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2020-2022 Microchip Technology Inc */
> +
> +/ {
> + fabric_clk3: fabric-clk3 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <62500000>;
> + };
> +
> + fabric_clk1: fabric-clk1 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <125000000>;
> + };
> +};
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
> new file mode 100644
> index 000000000000..1cad5b0d42e1
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
> @@ -0,0 +1,97 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2020-2022 Microchip Technology Inc */
> +
> +/dts-v1/;
> +
> +#include "mpfs.dtsi"
> +#include "mpfs-polarberry-fabric.dtsi"
> +
> +/* Clock frequency (in Hz) of the rtcclk */
> +#define MTIMER_FREQ 1000000
> +
> +/ {
> + model = "Sundance PolarBerry";
> + compatible = "sundance,polarberry", "microchip,mpfs";
> +
> + aliases {
> + ethernet0 = &mac1;
> + serial0 = &mmuart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + cpus {
> + timebase-frequency = <MTIMER_FREQ>;
> + };
> +
> + ddrc_cache_lo: memory@80000000 {
> + device_type = "memory";
> + reg = <0x0 0x80000000 0x0 0x2e000000>;
> + };
> +
> + ddrc_cache_hi: memory@1000000000 {
> + device_type = "memory";
> + reg = <0x10 0x00000000 0x0 0xC0000000>;
> + };
> +};
> +
> +/*
> + * phy0 is connected to mac0, but the port itself is on the (optional) carrier
> + * board.
> + */
> +&mac0 {
> + status = "disabled";
> + phy-mode = "sgmii";
> + phy-handle = <&phy0>;
nit: it makes it was easier recognizing the status if it's in the
same place all the time (for example as the last property)
like in &mmc below.
Though that may just be my preference ;-) .
The other option would be to adhere to stricter sorting
because right now status is neither in one place nor sorted.
> +};
> +
> +&mac1 {
> + status = "okay";
> + phy-mode = "sgmii";
> + phy-handle = <&phy1>;
nit (1): same as above
nit (2): blank line between properties and subnodes makes
everything more readable.
> + phy1: ethernet-phy@5 {
> + reg = <5>;
> + ti,fifo-depth = <0x01>;
> + };
nit: blank line?
Otherwise:
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> + phy0: ethernet-phy@4 {
> + reg = <4>;
> + ti,fifo-depth = <0x01>;
> + };
> +};
> +
> +&mbox {
> + status = "okay";
> +};
> +
> +&mmc {
> + bus-width = <4>;
> + disable-wp;
> + cap-sd-highspeed;
> + cap-mmc-highspeed;
> + card-detect-delay = <200>;
> + mmc-ddr-1_8v;
> + mmc-hs200-1_8v;
> + sd-uhs-sdr12;
> + sd-uhs-sdr25;
> + sd-uhs-sdr50;
> + sd-uhs-sdr104;
> + status = "okay";
> +};
> +
> +&mmuart0 {
> + status = "okay";
> +};
> +
> +&refclk {
> + clock-frequency = <125000000>;
> +};
> +
> +&rtc {
> + status = "okay";
> +};
> +
> +&syscontroller {
> + status = "okay";
> +};
>
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v4 8/8] riscv: dts: microchip: add the sundance polarberry
2022-05-09 11:10 ` Heiko Stübner
@ 2022-05-09 11:24 ` Conor.Dooley
2022-05-09 13:07 ` Heiko Stübner
0 siblings, 1 reply; 14+ messages in thread
From: Conor.Dooley @ 2022-05-09 11:24 UTC (permalink / raw)
To: heiko, krzk+dt, palmer, robh+dt, mail
Cc: Cyril.Jean, Daire.McNamara, paul.walmsley, aou, palmer, arnd,
devicetree, linux-kernel, linux-riscv
On 09/05/2022 12:10, Heiko Stübner wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Am Mittwoch, 4. Mai 2022, 22:30:52 CEST schrieb Conor Dooley:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> Add a minimal device tree for the PolarFire SoC based Sundance
>> PolarBerry.
>>
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>> ---
>> arch/riscv/boot/dts/microchip/Makefile | 1 +
>> .../dts/microchip/mpfs-polarberry-fabric.dtsi | 16 +++
>> .../boot/dts/microchip/mpfs-polarberry.dts | 97 +++++++++++++++++++
>> 3 files changed, 114 insertions(+)
>> create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
>> create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
>>
>> diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
>> index af3a5059b350..39aae7b04f1c 100644
>> --- a/arch/riscv/boot/dts/microchip/Makefile
>> +++ b/arch/riscv/boot/dts/microchip/Makefile
>> @@ -1,3 +1,4 @@
>> # SPDX-License-Identifier: GPL-2.0
>> dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
>> +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
>> obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
>> diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
>> new file mode 100644
>> index 000000000000..49380c428ec9
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
>> @@ -0,0 +1,16 @@
>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> +/* Copyright (c) 2020-2022 Microchip Technology Inc */
>> +
>> +/ {
>> + fabric_clk3: fabric-clk3 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <62500000>;
>> + };
>> +
>> + fabric_clk1: fabric-clk1 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <125000000>;
>> + };
>> +};
>> diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
>> new file mode 100644
>> index 000000000000..1cad5b0d42e1
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
>> @@ -0,0 +1,97 @@
>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> +/* Copyright (c) 2020-2022 Microchip Technology Inc */
>> +
>> +/dts-v1/;
>> +
>> +#include "mpfs.dtsi"
>> +#include "mpfs-polarberry-fabric.dtsi"
>> +
>> +/* Clock frequency (in Hz) of the rtcclk */
>> +#define MTIMER_FREQ 1000000
>> +
>> +/ {
>> + model = "Sundance PolarBerry";
>> + compatible = "sundance,polarberry", "microchip,mpfs";
>> +
>> + aliases {
>> + ethernet0 = &mac1;
>> + serial0 = &mmuart0;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + cpus {
>> + timebase-frequency = <MTIMER_FREQ>;
>> + };
>> +
>> + ddrc_cache_lo: memory@80000000 {
>> + device_type = "memory";
>> + reg = <0x0 0x80000000 0x0 0x2e000000>;
>> + };
>> +
>> + ddrc_cache_hi: memory@1000000000 {
>> + device_type = "memory";
>> + reg = <0x10 0x00000000 0x0 0xC0000000>;
>> + };
>> +};
>> +
>> +/*
>> + * phy0 is connected to mac0, but the port itself is on the (optional) carrier
>> + * board.
>> + */
>> +&mac0 {
>> + status = "disabled";
>> + phy-mode = "sgmii";
>> + phy-handle = <&phy0>;
>
> nit: it makes it was easier recognizing the status if it's in the
> same place all the time (for example as the last property)
> like in &mmc below.
>
> Though that may just be my preference ;-) .
> The other option would be to adhere to stricter sorting
> because right now status is neither in one place nor sorted.
My I had it in my head (and correct me if I am wrong please), that it is
okay to sort the phys after the status. It doesn't matter either way to
me, but there are plenty of dts that do it this way.
I don't care either way, so I am happy to change if those are bad examples
to follow!
>
>
>> +};
>> +
>> +&mac1 {
>> + status = "okay";
>> + phy-mode = "sgmii";
>> + phy-handle = <&phy1>;
>
> nit (1): same as above
> nit (2): blank line between properties and subnodes makes
> everything more readable.
Aye, not wrong. I'll fix this regardless of what happens with
the status ordering.
Thanks,
Conor.
>
>> + phy1: ethernet-phy@5 {
>> + reg = <5>;
>> + ti,fifo-depth = <0x01>;
>> + };
>
> nit: blank line?
>
> Otherwise:
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
>
>> + phy0: ethernet-phy@4 {
>> + reg = <4>;
>> + ti,fifo-depth = <0x01>;
>> + };
>> +};
>> +
>> +&mbox {
>> + status = "okay";
>> +};
>> +
>> +&mmc {
>> + bus-width = <4>;
>> + disable-wp;
>> + cap-sd-highspeed;
>> + cap-mmc-highspeed;
>> + card-detect-delay = <200>;
>> + mmc-ddr-1_8v;
>> + mmc-hs200-1_8v;
>> + sd-uhs-sdr12;
>> + sd-uhs-sdr25;
>> + sd-uhs-sdr50;
>> + sd-uhs-sdr104;
>> + status = "okay";
>> +};
>> +
>> +&mmuart0 {
>> + status = "okay";
>> +};
>> +
>> +&refclk {
>> + clock-frequency = <125000000>;
>> +};
>> +
>> +&rtc {
>> + status = "okay";
>> +};
>> +
>> +&syscontroller {
>> + status = "okay";
>> +};
>>
>
>
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v4 8/8] riscv: dts: microchip: add the sundance polarberry
2022-05-09 11:24 ` Conor.Dooley
@ 2022-05-09 13:07 ` Heiko Stübner
2022-05-09 13:23 ` Conor.Dooley
0 siblings, 1 reply; 14+ messages in thread
From: Heiko Stübner @ 2022-05-09 13:07 UTC (permalink / raw)
To: krzk+dt, palmer, robh+dt, mail, Conor.Dooley
Cc: Cyril.Jean, Daire.McNamara, paul.walmsley, aou, palmer, arnd,
devicetree, linux-kernel, linux-riscv
Am Montag, 9. Mai 2022, 13:24:12 CEST schrieb Conor.Dooley@microchip.com:
> On 09/05/2022 12:10, Heiko Stübner wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Am Mittwoch, 4. Mai 2022, 22:30:52 CEST schrieb Conor Dooley:
> >> From: Conor Dooley <conor.dooley@microchip.com>
> >>
> >> Add a minimal device tree for the PolarFire SoC based Sundance
> >> PolarBerry.
> >>
> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> >> ---
> >> arch/riscv/boot/dts/microchip/Makefile | 1 +
> >> .../dts/microchip/mpfs-polarberry-fabric.dtsi | 16 +++
> >> .../boot/dts/microchip/mpfs-polarberry.dts | 97 +++++++++++++++++++
> >> 3 files changed, 114 insertions(+)
> >> create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
> >> create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
> >>
> >> diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
> >> index af3a5059b350..39aae7b04f1c 100644
> >> --- a/arch/riscv/boot/dts/microchip/Makefile
> >> +++ b/arch/riscv/boot/dts/microchip/Makefile
> >> @@ -1,3 +1,4 @@
> >> # SPDX-License-Identifier: GPL-2.0
> >> dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
> >> +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
> >> obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
> >> diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
> >> new file mode 100644
> >> index 000000000000..49380c428ec9
> >> --- /dev/null
> >> +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
> >> @@ -0,0 +1,16 @@
> >> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> >> +/* Copyright (c) 2020-2022 Microchip Technology Inc */
> >> +
> >> +/ {
> >> + fabric_clk3: fabric-clk3 {
> >> + compatible = "fixed-clock";
> >> + #clock-cells = <0>;
> >> + clock-frequency = <62500000>;
> >> + };
> >> +
> >> + fabric_clk1: fabric-clk1 {
> >> + compatible = "fixed-clock";
> >> + #clock-cells = <0>;
> >> + clock-frequency = <125000000>;
> >> + };
> >> +};
> >> diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
> >> new file mode 100644
> >> index 000000000000..1cad5b0d42e1
> >> --- /dev/null
> >> +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
> >> @@ -0,0 +1,97 @@
> >> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> >> +/* Copyright (c) 2020-2022 Microchip Technology Inc */
> >> +
> >> +/dts-v1/;
> >> +
> >> +#include "mpfs.dtsi"
> >> +#include "mpfs-polarberry-fabric.dtsi"
> >> +
> >> +/* Clock frequency (in Hz) of the rtcclk */
> >> +#define MTIMER_FREQ 1000000
> >> +
> >> +/ {
> >> + model = "Sundance PolarBerry";
> >> + compatible = "sundance,polarberry", "microchip,mpfs";
> >> +
> >> + aliases {
> >> + ethernet0 = &mac1;
> >> + serial0 = &mmuart0;
> >> + };
> >> +
> >> + chosen {
> >> + stdout-path = "serial0:115200n8";
> >> + };
> >> +
> >> + cpus {
> >> + timebase-frequency = <MTIMER_FREQ>;
> >> + };
> >> +
> >> + ddrc_cache_lo: memory@80000000 {
> >> + device_type = "memory";
> >> + reg = <0x0 0x80000000 0x0 0x2e000000>;
> >> + };
> >> +
> >> + ddrc_cache_hi: memory@1000000000 {
> >> + device_type = "memory";
> >> + reg = <0x10 0x00000000 0x0 0xC0000000>;
> >> + };
> >> +};
> >> +
> >> +/*
> >> + * phy0 is connected to mac0, but the port itself is on the (optional) carrier
> >> + * board.
> >> + */
> >> +&mac0 {
> >> + status = "disabled";
> >> + phy-mode = "sgmii";
> >> + phy-handle = <&phy0>;
> >
> > nit: it makes it was easier recognizing the status if it's in the
> > same place all the time (for example as the last property)
> > like in &mmc below.
> >
> > Though that may just be my preference ;-) .
> > The other option would be to adhere to stricter sorting
> > because right now status is neither in one place nor sorted.
>
> My I had it in my head (and correct me if I am wrong please), that it is
> okay to sort the phys after the status. It doesn't matter either way to
> me, but there are plenty of dts that do it this way.
>
> I don't care either way, so I am happy to change if those are bad examples
> to follow!
I guess which order to follow really is more a matter of taste and I
don't think there is a definitive rulebook on what belongs where ;-) .
Though from past experience I do know that it makes reading devicetrees
easier when you know which property to expect in which place - especially
when their number increases and right now you have status above here,
and below everything else in the mmc node for example.
In the end Palmer might not care that much about tiny odering
differences, but I do think following one scheme is definitively an
advantage over mixing different ones.
Heiko
> >> +};
> >> +
> >> +&mac1 {
> >> + status = "okay";
> >> + phy-mode = "sgmii";
> >> + phy-handle = <&phy1>;
> >
> > nit (1): same as above
> > nit (2): blank line between properties and subnodes makes
> > everything more readable.
>
> Aye, not wrong. I'll fix this regardless of what happens with
> the status ordering.
> Thanks,
> Conor.
>
> >
> >> + phy1: ethernet-phy@5 {
> >> + reg = <5>;
> >> + ti,fifo-depth = <0x01>;
> >> + };
> >
> > nit: blank line?
> >
> > Otherwise:
> > Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> >
> >> + phy0: ethernet-phy@4 {
> >> + reg = <4>;
> >> + ti,fifo-depth = <0x01>;
> >> + };
> >> +};
> >> +
> >> +&mbox {
> >> + status = "okay";
> >> +};
> >> +
> >> +&mmc {
> >> + bus-width = <4>;
> >> + disable-wp;
> >> + cap-sd-highspeed;
> >> + cap-mmc-highspeed;
> >> + card-detect-delay = <200>;
> >> + mmc-ddr-1_8v;
> >> + mmc-hs200-1_8v;
> >> + sd-uhs-sdr12;
> >> + sd-uhs-sdr25;
> >> + sd-uhs-sdr50;
> >> + sd-uhs-sdr104;
> >> + status = "okay";
> >> +};
> >> +
> >> +&mmuart0 {
> >> + status = "okay";
> >> +};
> >> +
> >> +&refclk {
> >> + clock-frequency = <125000000>;
> >> +};
> >> +
> >> +&rtc {
> >> + status = "okay";
> >> +};
> >> +
> >> +&syscontroller {
> >> + status = "okay";
> >> +};
> >>
> >
> >
> >
> >
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v4 8/8] riscv: dts: microchip: add the sundance polarberry
2022-05-09 13:07 ` Heiko Stübner
@ 2022-05-09 13:23 ` Conor.Dooley
0 siblings, 0 replies; 14+ messages in thread
From: Conor.Dooley @ 2022-05-09 13:23 UTC (permalink / raw)
To: heiko, krzk+dt, palmer, robh+dt, Conor.Dooley
Cc: Cyril.Jean, Daire.McNamara, paul.walmsley, aou, palmer, arnd,
devicetree, linux-kernel, linux-riscv
On 09/05/2022 14:07, Heiko Stübner wrote:
> Am Montag, 9. Mai 2022, 13:24:12 CEST schrieb Conor.Dooley@microchip.com:
>> On 09/05/2022 12:10, Heiko Stübner wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> Am Mittwoch, 4. Mai 2022, 22:30:52 CEST schrieb Conor Dooley:
>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>
>>>> Add a minimal device tree for the PolarFire SoC based Sundance
>>>> PolarBerry.
>>>>
>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>> ---
>>>> arch/riscv/boot/dts/microchip/Makefile | 1 +
>>>> .../dts/microchip/mpfs-polarberry-fabric.dtsi | 16 +++
>>>> .../boot/dts/microchip/mpfs-polarberry.dts | 97 +++++++++++++++++++
>>>> 3 files changed, 114 insertions(+)
>>>> create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
>>>> create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
>>>>
>>>> diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
>>>> index af3a5059b350..39aae7b04f1c 100644
>>>> --- a/arch/riscv/boot/dts/microchip/Makefile
>>>> +++ b/arch/riscv/boot/dts/microchip/Makefile
>>>> @@ -1,3 +1,4 @@
>>>> # SPDX-License-Identifier: GPL-2.0
>>>> dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
>>>> +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
>>>> obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
>>>> diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
>>>> new file mode 100644
>>>> index 000000000000..49380c428ec9
>>>> --- /dev/null
>>>> +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
>>>> @@ -0,0 +1,16 @@
>>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>>> +/* Copyright (c) 2020-2022 Microchip Technology Inc */
>>>> +
>>>> +/ {
>>>> + fabric_clk3: fabric-clk3 {
>>>> + compatible = "fixed-clock";
>>>> + #clock-cells = <0>;
>>>> + clock-frequency = <62500000>;
>>>> + };
>>>> +
>>>> + fabric_clk1: fabric-clk1 {
>>>> + compatible = "fixed-clock";
>>>> + #clock-cells = <0>;
>>>> + clock-frequency = <125000000>;
>>>> + };
>>>> +};
>>>> diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
>>>> new file mode 100644
>>>> index 000000000000..1cad5b0d42e1
>>>> --- /dev/null
>>>> +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
>>>> @@ -0,0 +1,97 @@
>>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>>> +/* Copyright (c) 2020-2022 Microchip Technology Inc */
>>>> +
>>>> +/dts-v1/;
>>>> +
>>>> +#include "mpfs.dtsi"
>>>> +#include "mpfs-polarberry-fabric.dtsi"
>>>> +
>>>> +/* Clock frequency (in Hz) of the rtcclk */
>>>> +#define MTIMER_FREQ 1000000
>>>> +
>>>> +/ {
>>>> + model = "Sundance PolarBerry";
>>>> + compatible = "sundance,polarberry", "microchip,mpfs";
>>>> +
>>>> + aliases {
>>>> + ethernet0 = &mac1;
>>>> + serial0 = &mmuart0;
>>>> + };
>>>> +
>>>> + chosen {
>>>> + stdout-path = "serial0:115200n8";
>>>> + };
>>>> +
>>>> + cpus {
>>>> + timebase-frequency = <MTIMER_FREQ>;
>>>> + };
>>>> +
>>>> + ddrc_cache_lo: memory@80000000 {
>>>> + device_type = "memory";
>>>> + reg = <0x0 0x80000000 0x0 0x2e000000>;
>>>> + };
>>>> +
>>>> + ddrc_cache_hi: memory@1000000000 {
>>>> + device_type = "memory";
>>>> + reg = <0x10 0x00000000 0x0 0xC0000000>;
>>>> + };
>>>> +};
>>>> +
>>>> +/*
>>>> + * phy0 is connected to mac0, but the port itself is on the (optional) carrier
>>>> + * board.
>>>> + */
>>>> +&mac0 {
>>>> + status = "disabled";
>>>> + phy-mode = "sgmii";
>>>> + phy-handle = <&phy0>;
>>>
>>> nit: it makes it was easier recognizing the status if it's in the
>>> same place all the time (for example as the last property)
>>> like in &mmc below.
>>>
>>> Though that may just be my preference ;-) .
>>> The other option would be to adhere to stricter sorting
>>> because right now status is neither in one place nor sorted.
>>
>> My I had it in my head (and correct me if I am wrong please), that it is
>> okay to sort the phys after the status. It doesn't matter either way to
>> me, but there are plenty of dts that do it this way.
>>
>> I don't care either way, so I am happy to change if those are bad examples
>> to follow!
>
> I guess which order to follow really is more a matter of taste and I
> don't think there is a definitive rulebook on what belongs where ;-) .
>
> Though from past experience I do know that it makes reading devicetrees
> easier when you know which property to expect in which place - especially
> when their number increases and right now you have status above here,
> and below everything else in the mmc node for example.
>
> In the end Palmer might not care that much about tiny odering
> differences, but I do think following one scheme is definitively an
> advantage over mixing different ones.
Aye. I guess I will respin with the statuses at the end. If someone has
a problem, they're always free to raise an objection ;) Really doesn't
matter to me & if it makes reading the dt easier for some...
>
>
> Heiko
>
>
>>>> +};
>>>> +
>>>> +&mac1 {
>>>> + status = "okay";
>>>> + phy-mode = "sgmii";
>>>> + phy-handle = <&phy1>;
>>>
>>> nit (1): same as above
>>> nit (2): blank line between properties and subnodes makes
>>> everything more readable.
>>
>> Aye, not wrong. I'll fix this regardless of what happens with
>> the status ordering.
>> Thanks,
>> Conor.
>>
>>>
>>>> + phy1: ethernet-phy@5 {
>>>> + reg = <5>;
>>>> + ti,fifo-depth = <0x01>;
>>>> + };
>>>
>>> nit: blank line?
>>>
>>> Otherwise:
>>> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
>>>
>>>> + phy0: ethernet-phy@4 {
>>>> + reg = <4>;
>>>> + ti,fifo-depth = <0x01>;
>>>> + };
>>>> +};
>>>> +
>>>> +&mbox {
>>>> + status = "okay";
>>>> +};
>>>> +
>>>> +&mmc {
>>>> + bus-width = <4>;
>>>> + disable-wp;
>>>> + cap-sd-highspeed;
>>>> + cap-mmc-highspeed;
>>>> + card-detect-delay = <200>;
>>>> + mmc-ddr-1_8v;
>>>> + mmc-hs200-1_8v;
>>>> + sd-uhs-sdr12;
>>>> + sd-uhs-sdr25;
>>>> + sd-uhs-sdr50;
>>>> + sd-uhs-sdr104;
>>>> + status = "okay";
>>>> +};
>>>> +
>>>> +&mmuart0 {
>>>> + status = "okay";
>>>> +};
>>>> +
>>>> +&refclk {
>>>> + clock-frequency = <125000000>;
>>>> +};
>>>> +
>>>> +&rtc {
>>>> + status = "okay";
>>>> +};
>>>> +
>>>> +&syscontroller {
>>>> + status = "okay";
>>>> +};
>>>>
>>>
>>>
>>>
>>>
>>
>>
>
>
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread