[PATCH v2 0/3] soc: qcom: llcc: Add support for Glymur SoC

[PATCH v2 0/3] soc: qcom: llcc: Add support for Glymur SoC

[Pankaj Patil]

Glymur SoC uses the Last Level Cache Controller (LLCC) as its
system cache controller, update the device-tree bindings to allow
maximum of 14 registers for llcc block since GLymur has 12 llcc base
register regions and an additional AND, OR broadcast base register.
Updated SCT configuration data in the LLCC driver.

Enabled additional use case IDs defined in
include/linux/soc/qcom/llcc-qcom.h:

OOBM_NS
OOBM_S
VIDSC_VSP1
PCIE_TCU

Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
Changes in v2:
- Updated dt-bindings for maximum no of registers to be 14
- Re-ordered the fix alignment patch to before adding a new entry for Glymur
- Squashed commit for enablement of usecase id and driver changes
- Link to v1: https://lore.kernel.org/all/20251121-glymur_llcc_enablement-v1-0-336b851b8dcb@oss.qualcomm.com/

---
Pankaj Patil (3):
      dt-bindings: cache: qcom,llcc: Document Glymur LLCC block
      soc: qcom: llcc: Fix usecase id macro alignment
      soc: qcom: llcc-qcom: Add support for Glymur

 .../devicetree/bindings/cache/qcom,llcc.yaml       |  47 ++++-
 drivers/soc/qcom/llcc-qcom.c                       | 207 +++++++++++++++++++++
 include/linux/soc/qcom/llcc-qcom.h                 | 152 +++++++--------
 3 files changed, 330 insertions(+), 76 deletions(-)
---
base-commit: d724c6f85e80a23ed46b7ebc6e38b527c09d64f5
change-id: 20251029-glymur_llcc_enablement-6a812c08f4c1

Best regards,
-- 
Pankaj Patil <pankaj.patil@oss.qualcomm.com>

[PATCH v2 1/3] dt-bindings: cache: qcom,llcc: Document Glymur LLCC block

[Pankaj Patil]

Document the Last Level Cache Controller on Glymur SoC
Glymur LLCC has 12 base register regions and an additional AND, OR
broadcast region, total 14 register regions
Increase maxItems for reg and reg-names to allow 14 entries for Glymur

Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
 .../devicetree/bindings/cache/qcom,llcc.yaml       | 47 +++++++++++++++++++++-
 1 file changed, 45 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
index a620a2ff5c56..4e99c405aea3 100644
--- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
+++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
@@ -20,6 +20,7 @@ description: |
 properties:
   compatible:
     enum:
+      - qcom,glymur-llcc
       - qcom,ipq5424-llcc
       - qcom,kaanapali-llcc
       - qcom,qcs615-llcc
@@ -46,11 +47,11 @@ properties:
 
   reg:
     minItems: 1
-    maxItems: 10
+    maxItems: 14
 
   reg-names:
     minItems: 1
-    maxItems: 10
+    maxItems: 14
 
   interrupts:
     maxItems: 1
@@ -84,6 +85,48 @@ allOf:
           items:
             - const: llcc0_base
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,glymur-llcc
+    then:
+      properties:
+        reg:
+          items:
+            - description: LLCC0 base register region
+            - description: LLCC1 base register region
+            - description: LLCC2 base register region
+            - description: LLCC3 base register region
+            - description: LLCC4 base register region
+            - description: LLCC5 base register region
+            - description: LLCC6 base register region
+            - description: LLCC7 base register region
+            - description: LLCC8 base register region
+            - description: LLCC9 base register region
+            - description: LLCC10 base register region
+            - description: LLCC11 base register region
+            - description: LLCC broadcast base register region
+            - description: LLCC broadcast AND register region
+        reg-names:
+          items:
+            - const: llcc0_base
+            - const: llcc1_base
+            - const: llcc2_base
+            - const: llcc3_base
+            - const: llcc4_base
+            - const: llcc5_base
+            - const: llcc6_base
+            - const: llcc7_base
+            - const: llcc7_base
+            - const: llcc8_base
+            - const: llcc9_base
+            - const: llcc10_base
+            - const: llcc11_base
+            - const: llcc_broadcast_base
+            - const: llcc_broadcast_and_base
+
   - if:
       properties:
         compatible:

-- 
2.34.1

Re: [PATCH v2 1/3] dt-bindings: cache: qcom,llcc: Document Glymur LLCC block

[Krzysztof Kozlowski]

On Tue, Nov 25, 2025 at 02:46:22PM +0530, Pankaj Patil wrote:
> Document the Last Level Cache Controller on Glymur SoC
> Glymur LLCC has 12 base register regions and an additional AND, OR
> broadcast region, total 14 register regions
> Increase maxItems for reg and reg-names to allow 14 entries for Glymur
> 
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
>  .../devicetree/bindings/cache/qcom,llcc.yaml       | 47 +++++++++++++++++++++-
>  1 file changed, 45 insertions(+), 2 deletions(-)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

[PATCH v2 2/3] soc: qcom: llcc: Fix usecase id macro alignment

[Pankaj Patil]

Aligned macro values for usecase id along the column length

Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
 include/linux/soc/qcom/llcc-qcom.h | 148 ++++++++++++++++++-------------------
 1 file changed, 74 insertions(+), 74 deletions(-)

diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
index 0287f9182c4d..c52464262ab3 100644
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -8,80 +8,80 @@
 #ifndef __LLCC_QCOM__
 #define __LLCC_QCOM__
 
-#define LLCC_CPUSS       1
-#define LLCC_VIDSC0      2
-#define LLCC_VIDSC1      3
-#define LLCC_ROTATOR     4
-#define LLCC_VOICE       5
-#define LLCC_AUDIO       6
-#define LLCC_MDMHPGRW    7
-#define LLCC_MDM         8
-#define LLCC_MODHW       9
-#define LLCC_CMPT        10
-#define LLCC_GPUHTW      11
-#define LLCC_GPU         12
-#define LLCC_MMUHWT      13
-#define LLCC_CMPTDMA     15
-#define LLCC_DISP        16
-#define LLCC_VIDFW       17
-#define LLCC_CAMFW       18
-#define LLCC_MDMHPFX     20
-#define LLCC_MDMPNG      21
-#define LLCC_AUDHW       22
-#define LLCC_NPU         23
-#define LLCC_WLHW        24
-#define LLCC_PIMEM       25
-#define LLCC_ECC         26
-#define LLCC_CVP         28
-#define LLCC_MODPE       29
-#define LLCC_APTCM       30
-#define LLCC_WRCACHE     31
-#define LLCC_CVPFW       32
-#define LLCC_CPUSS1      33
-#define LLCC_CAMEXP0     34
-#define LLCC_CPUMTE      35
-#define LLCC_CPUHWT      36
-#define LLCC_MDMCLAD2    37
-#define LLCC_CAMEXP1     38
-#define LLCC_CMPTHCP     39
-#define LLCC_LCPDARE     40
-#define LLCC_AENPU       45
-#define LLCC_ISLAND1     46
-#define LLCC_ISLAND2     47
-#define LLCC_ISLAND3     48
-#define LLCC_ISLAND4     49
-#define LLCC_CAMEXP2	 50
-#define LLCC_CAMEXP3	 51
-#define LLCC_CAMEXP4	 52
-#define LLCC_DISP_WB	 53
-#define LLCC_DISP_1	 54
-#define LLCC_VIEYE	 57
-#define LLCC_VIDPTH	 58
-#define LLCC_GPUMV	 59
-#define LLCC_EVA_LEFT	 60
-#define LLCC_EVA_RIGHT	 61
-#define LLCC_EVAGAIN	 62
-#define LLCC_VIPTH	 63
-#define LLCC_VIDVSP	 64
-#define LLCC_DISP_LEFT	 65
-#define LLCC_DISP_RIGHT	 66
-#define LLCC_EVCS_LEFT	 67
-#define LLCC_EVCS_RIGHT	 68
-#define LLCC_SPAD	 69
-#define LLCC_VIDDEC	 70
-#define LLCC_CAMOFE	 71
-#define LLCC_CAMRTIP	 72
-#define LLCC_CAMSRTIP	 73
-#define LLCC_CAMRTRF	 74
-#define LLCC_CAMSRTRF	 75
-#define LLCC_VIDEO_APV	 83
-#define LLCC_COMPUTE1	 87
-#define LLCC_CPUSS_OPP	 88
-#define LLCC_CPUSSMPAM	 89
-#define LLCC_CAM_IPE_STROV	 92
-#define LLCC_CAM_OFE_STROV	 93
-#define LLCC_CPUSS_HEU	 94
-#define LLCC_MDM_PNG_FIXED	 100
+#define LLCC_CPUSS         1
+#define LLCC_VIDSC0        2
+#define LLCC_VIDSC1        3
+#define LLCC_ROTATOR       4
+#define LLCC_VOICE         5
+#define LLCC_AUDIO         6
+#define LLCC_MDMHPGRW      7
+#define LLCC_MDM           8
+#define LLCC_MODHW         9
+#define LLCC_CMPT          10
+#define LLCC_GPUHTW        11
+#define LLCC_GPU           12
+#define LLCC_MMUHWT        13
+#define LLCC_CMPTDMA       15
+#define LLCC_DISP          16
+#define LLCC_VIDFW         17
+#define LLCC_CAMFW         18
+#define LLCC_MDMHPFX       20
+#define LLCC_MDMPNG        21
+#define LLCC_AUDHW         22
+#define LLCC_NPU           23
+#define LLCC_WLHW          24
+#define LLCC_PIMEM         25
+#define LLCC_ECC           26
+#define LLCC_CVP           28
+#define LLCC_MODPE         29
+#define LLCC_APTCM         30
+#define LLCC_WRCACHE       31
+#define LLCC_CVPFW         32
+#define LLCC_CPUSS1        33
+#define LLCC_CAMEXP0       34
+#define LLCC_CPUMTE        35
+#define LLCC_CPUHWT        36
+#define LLCC_MDMCLAD2      37
+#define LLCC_CAMEXP1       38
+#define LLCC_CMPTHCP       39
+#define LLCC_LCPDARE       40
+#define LLCC_AENPU         45
+#define LLCC_ISLAND1       46
+#define LLCC_ISLAND2       47
+#define LLCC_ISLAND3       48
+#define LLCC_ISLAND4       49
+#define LLCC_CAMEXP2       50
+#define LLCC_CAMEXP3       51
+#define LLCC_CAMEXP4       52
+#define LLCC_DISP_WB       53
+#define LLCC_DISP_1        54
+#define LLCC_VIEYE         57
+#define LLCC_VIDPTH        58
+#define LLCC_GPUMV         59
+#define LLCC_EVA_LEFT      60
+#define LLCC_EVA_RIGHT     61
+#define LLCC_EVAGAIN       62
+#define LLCC_VIPTH         63
+#define LLCC_VIDVSP        64
+#define LLCC_DISP_LEFT     65
+#define LLCC_DISP_RIGHT    66
+#define LLCC_EVCS_LEFT     67
+#define LLCC_EVCS_RIGHT    68
+#define LLCC_SPAD          69
+#define LLCC_VIDDEC        70
+#define LLCC_CAMOFE        71
+#define LLCC_CAMRTIP       72
+#define LLCC_CAMSRTIP      73
+#define LLCC_CAMRTRF       74
+#define LLCC_CAMSRTRF      75
+#define LLCC_VIDEO_APV     83
+#define LLCC_COMPUTE1      87
+#define LLCC_CPUSS_OPP     88
+#define LLCC_CPUSSMPAM     89
+#define LLCC_CAM_IPE_STROV 92
+#define LLCC_CAM_OFE_STROV 93
+#define LLCC_CPUSS_HEU     94
+#define LLCC_MDM_PNG_FIXED 100
 
 /**
  * struct llcc_slice_desc - Cache slice descriptor

-- 
2.34.1

Re: [PATCH v2 2/3] soc: qcom: llcc: Fix usecase id macro alignment

[Krzysztof Kozlowski]

On Tue, Nov 25, 2025 at 02:46:23PM +0530, Pankaj Patil wrote:
> Aligned macro values for usecase id along the column length
> -#define LLCC_CAMOFE	 71
> -#define LLCC_CAMRTIP	 72
> -#define LLCC_CAMSRTIP	 73
> -#define LLCC_CAMRTRF	 74
> -#define LLCC_CAMSRTRF	 75
> -#define LLCC_VIDEO_APV	 83
> -#define LLCC_COMPUTE1	 87
> -#define LLCC_CPUSS_OPP	 88
> -#define LLCC_CPUSSMPAM	 89
> -#define LLCC_CAM_IPE_STROV	 92
> -#define LLCC_CAM_OFE_STROV	 93
> -#define LLCC_CPUSS_HEU	 94
> -#define LLCC_MDM_PNG_FIXED	 100
> +#define LLCC_CPUSS         1
> +#define LLCC_VIDSC0        2
> +#define LLCC_VIDSC1        3
> +#define LLCC_ROTATOR       4
> +#define LLCC_VOICE         5

This does not look right - you still have here spaces, so nothing fixed.

I don't think this change is useful. You replaced one poor alignment
into another poor alignment, so IMO better not to touch this at all.

Best regards,
Krzysztof

Re: [PATCH v2 2/3] soc: qcom: llcc: Fix usecase id macro alignment

[Pankaj Patil]

On 11/26/2025 2:29 PM, Krzysztof Kozlowski wrote:
> On Tue, Nov 25, 2025 at 02:46:23PM +0530, Pankaj Patil wrote:
>> Aligned macro values for usecase id along the column length
>> -#define LLCC_CAMOFE	 71
>> -#define LLCC_CAMRTIP	 72
>> -#define LLCC_CAMSRTIP	 73
>> -#define LLCC_CAMRTRF	 74
>> -#define LLCC_CAMSRTRF	 75
>> -#define LLCC_VIDEO_APV	 83
>> -#define LLCC_COMPUTE1	 87
>> -#define LLCC_CPUSS_OPP	 88
>> -#define LLCC_CPUSSMPAM	 89
>> -#define LLCC_CAM_IPE_STROV	 92
>> -#define LLCC_CAM_OFE_STROV	 93
>> -#define LLCC_CPUSS_HEU	 94
>> -#define LLCC_MDM_PNG_FIXED	 100
>> +#define LLCC_CPUSS         1
>> +#define LLCC_VIDSC0        2
>> +#define LLCC_VIDSC1        3
>> +#define LLCC_ROTATOR       4
>> +#define LLCC_VOICE         5
> This does not look right - you still have here spaces, so nothing fixed.
>
> I don't think this change is useful. You replaced one poor alignment
> into another poor alignment, so IMO better not to touch this at all.
>
> Best regards,
> Krzysztof
>
Sure, Will drop this patch in next revision

Re: [PATCH v2 2/3] soc: qcom: llcc: Fix usecase id macro alignment

[Bjorn Andersson]

On Wed, Nov 26, 2025 at 05:08:35PM +0530, Pankaj Patil wrote:
> On 11/26/2025 2:29 PM, Krzysztof Kozlowski wrote:
> > On Tue, Nov 25, 2025 at 02:46:23PM +0530, Pankaj Patil wrote:
> >> Aligned macro values for usecase id along the column length
> >> -#define LLCC_CAMOFE	 71
> >> -#define LLCC_CAMRTIP	 72
> >> -#define LLCC_CAMSRTIP	 73
> >> -#define LLCC_CAMRTRF	 74
> >> -#define LLCC_CAMSRTRF	 75
> >> -#define LLCC_VIDEO_APV	 83
> >> -#define LLCC_COMPUTE1	 87
> >> -#define LLCC_CPUSS_OPP	 88
> >> -#define LLCC_CPUSSMPAM	 89
> >> -#define LLCC_CAM_IPE_STROV	 92
> >> -#define LLCC_CAM_OFE_STROV	 93
> >> -#define LLCC_CPUSS_HEU	 94
> >> -#define LLCC_MDM_PNG_FIXED	 100
> >> +#define LLCC_CPUSS         1
> >> +#define LLCC_VIDSC0        2
> >> +#define LLCC_VIDSC1        3
> >> +#define LLCC_ROTATOR       4
> >> +#define LLCC_VOICE         5
> > This does not look right - you still have here spaces, so nothing fixed.
> >
> > I don't think this change is useful. You replaced one poor alignment
> > into another poor alignment, so IMO better not to touch this at all.
> >
> > Best regards,
> > Krzysztof
> >
> Sure, Will drop this patch in next revision
> 

No need to send a new version unless you get any additional feedback on
the two useful patches.

Regards,
Bjorn

Re: [PATCH v2 2/3] soc: qcom: llcc: Fix usecase id macro alignment

[Krzysztof Kozlowski]

On 26/11/2025 12:38, Pankaj Patil wrote:
> On 11/26/2025 2:29 PM, Krzysztof Kozlowski wrote:
>> On Tue, Nov 25, 2025 at 02:46:23PM +0530, Pankaj Patil wrote:
>>> Aligned macro values for usecase id along the column length
>>> -#define LLCC_CAMOFE	 71
>>> -#define LLCC_CAMRTIP	 72
>>> -#define LLCC_CAMSRTIP	 73
>>> -#define LLCC_CAMRTRF	 74
>>> -#define LLCC_CAMSRTRF	 75
>>> -#define LLCC_VIDEO_APV	 83
>>> -#define LLCC_COMPUTE1	 87
>>> -#define LLCC_CPUSS_OPP	 88
>>> -#define LLCC_CPUSSMPAM	 89
>>> -#define LLCC_CAM_IPE_STROV	 92
>>> -#define LLCC_CAM_OFE_STROV	 93
>>> -#define LLCC_CPUSS_HEU	 94
>>> -#define LLCC_MDM_PNG_FIXED	 100
>>> +#define LLCC_CPUSS         1
>>> +#define LLCC_VIDSC0        2
>>> +#define LLCC_VIDSC1        3
>>> +#define LLCC_ROTATOR       4
>>> +#define LLCC_VOICE         5
>> This does not look right - you still have here spaces, so nothing fixed.
>>
>> I don't think this change is useful. You replaced one poor alignment
>> into another poor alignment, so IMO better not to touch this at all.
>>
>> Best regards,
>> Krzysztof
>>
> Sure, Will drop this patch in next revision

If fixing this, fix correctly, so these should be tabs accommodating
future IDs, so you won't be doing the same every 3 months.

But to me it is a bit of churn, does not improve readability and
actually affects negatively git blame and backporting, so I would
propose to drop it.


Best regards,
Krzysztof

[PATCH v2 3/3] soc: qcom: llcc-qcom: Add support for Glymur

[Pankaj Patil]

Add system cache table(SCT) and configs for Glymur SoC
Updated the list of usecase id's to enable additional clients for Glymur

Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
 drivers/soc/qcom/llcc-qcom.c       | 207 +++++++++++++++++++++++++++++++++++++
 include/linux/soc/qcom/llcc-qcom.h |   4 +
 2 files changed, 211 insertions(+)

diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 13e174267294..1abfda7a58f2 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -182,6 +182,197 @@ enum llcc_reg_offset {
 	LLCC_TRP_WRS_CACHEABLE_EN,
 };
 
+static const struct llcc_slice_config glymur_data[] = {
+	{
+		.usecase_id = LLCC_CPUSS,
+		.slice_id = 1,
+		.max_cap = 7680,
+		.priority = 1,
+		.bonus_ways = 0xFFF,
+		.res_ways = 0x0,
+		.vict_prio = true,
+		.activate_on_init = true,
+	}, {
+		.usecase_id = LLCC_VIDSC0,
+		.slice_id = 2,
+		.max_cap = 512,
+		.priority = 3,
+		.fixed_size = true,
+		.bonus_ways = 0xFFF,
+		.res_ways = 0x0,
+		.vict_prio = true,
+	}, {
+		.usecase_id = LLCC_AUDIO,
+		.slice_id = 6,
+		.max_cap = 1024,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xFFF,
+		.res_ways = 0x0,
+		.vict_prio = true,
+	}, {
+		.usecase_id = LLCC_VIDSC1,
+		.slice_id = 4,
+		.max_cap = 512,
+		.priority = 3,
+		.fixed_size = true,
+		.bonus_ways = 0xFFF,
+		.res_ways = 0x0,
+		.vict_prio = true,
+	}, {
+		.usecase_id = LLCC_CMPT,
+		.slice_id = 10,
+		.max_cap = 7680,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xFFF,
+		.res_ways = 0x0,
+		.vict_prio = true,
+	}, {
+		.usecase_id = LLCC_GPUHTW,
+		.slice_id = 11,
+		.max_cap = 512,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xFFF,
+		.res_ways = 0x0,
+		.vict_prio = true,
+	}, {
+		.usecase_id = LLCC_GPU,
+		.slice_id = 9,
+		.max_cap = 7680,
+		.priority = 1,
+		.bonus_ways = 0xFFF,
+		.res_ways = 0x0,
+		.write_scid_en = true,
+		.write_scid_cacheable_en = true,
+		.stale_en = true,
+		.vict_prio = true,
+	}, {
+		.usecase_id = LLCC_MMUHWT,
+		.slice_id = 18,
+		.max_cap = 768,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xFFF,
+		.res_ways = 0x0,
+		.vict_prio = true,
+		.activate_on_init = true,
+	}, {
+		.usecase_id = LLCC_AUDHW,
+		.slice_id = 22,
+		.max_cap = 1024,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xFFF,
+		.res_ways = 0x0,
+		.vict_prio = true,
+	}, {
+		.usecase_id = LLCC_CVP,
+		.slice_id = 8,
+		.max_cap = 64,
+		.priority = 3,
+		.fixed_size = true,
+		.bonus_ways = 0xFFF,
+		.res_ways = 0x0,
+		.vict_prio = true,
+	}, {
+		.usecase_id = LLCC_WRCACHE,
+		.slice_id = 31,
+		.max_cap = 1536,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xFFF,
+		.res_ways = 0x0,
+		.vict_prio = true,
+		.activate_on_init = true,
+	}, {
+		.usecase_id = LLCC_CMPTHCP,
+		.slice_id = 17,
+		.max_cap = 256,
+		.priority = 3,
+		.fixed_size = true,
+		.bonus_ways = 0xFFF,
+		.res_ways = 0x0,
+		.vict_prio = true,
+	}, {
+		.usecase_id = LLCC_LCPDARE,
+		.slice_id = 30,
+		.max_cap = 768,
+		.priority = 3,
+		.fixed_size = true,
+		.bonus_ways = 0xFFF,
+		.res_ways = 0x0,
+		.alloc_oneway_en = true,
+		.vict_prio = true,
+		.activate_on_init = true,
+	}, {
+		.usecase_id = LLCC_AENPU,
+		.slice_id = 3,
+		.max_cap = 3072,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xFFF,
+		.res_ways = 0x0,
+		.cache_mode = 2,
+		.vict_prio = true,
+	}, {
+		.usecase_id = LLCC_ISLAND1,
+		.slice_id = 12,
+		.max_cap = 5632,
+		.priority = 7,
+		.fixed_size = true,
+		.bonus_ways = 0x0,
+		.res_ways = 0x7FF,
+		.vict_prio = true,
+	}, {
+		.usecase_id = LLCC_VIDVSP,
+		.slice_id = 28,
+		.max_cap = 256,
+		.priority = 3,
+		.fixed_size = true,
+		.bonus_ways = 0xFFF,
+		.res_ways = 0x0,
+		.vict_prio = true,
+	}, {
+		.usecase_id = LLCC_OOBM_NS,
+		.slice_id = 5,
+		.max_cap = 512,
+		.priority = 1,
+		.bonus_ways = 0xFFF,
+		.res_ways = 0x0,
+		.vict_prio = true,
+	}, {
+		.usecase_id = LLCC_CPUSS_OPP,
+		.slice_id = 32,
+		.max_cap = 0,
+		.fixed_size = true,
+		.bonus_ways = 0x0,
+		.res_ways = 0x0,
+		.vict_prio = true,
+		.activate_on_init = true,
+	}, {
+		.usecase_id = LLCC_PCIE_TCU,
+		.slice_id = 19,
+		.max_cap = 256,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xFFF,
+		.res_ways = 0x0,
+		.vict_prio = true,
+		.activate_on_init = true,
+	}, {
+		.usecase_id = LLCC_VIDSC_VSP1,
+		.slice_id = 29,
+		.max_cap = 256,
+		.priority = 3,
+		.fixed_size = true,
+		.bonus_ways = 0xFFF,
+		.res_ways = 0x0,
+		.vict_prio = true,
+	}
+};
+
 static const struct llcc_slice_config ipq5424_data[] =  {
 	{
 		.usecase_id = LLCC_CPUSS,
@@ -3872,6 +4063,16 @@ static const struct qcom_llcc_config kaanapali_cfg[] = {
 	},
 };
 
+static const struct qcom_llcc_config glymur_cfg[] = {
+	{
+		.sct_data	= glymur_data,
+		.size		= ARRAY_SIZE(glymur_data),
+		.reg_offset	= llcc_v6_reg_offset,
+		.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+		.no_edac	= true,
+	},
+};
+
 static const struct qcom_llcc_config qcs615_cfg[] = {
 	{
 		.sct_data	= qcs615_data,
@@ -4103,6 +4304,11 @@ static const struct qcom_sct_config kaanapali_cfgs = {
 	.num_config	= ARRAY_SIZE(kaanapali_cfg),
 };
 
+static const struct qcom_sct_config glymur_cfgs = {
+	.llcc_config	= glymur_cfg,
+	.num_config	= ARRAY_SIZE(glymur_cfg),
+};
+
 static const struct qcom_sct_config qcs615_cfgs = {
 	.llcc_config	= qcs615_cfg,
 	.num_config	= ARRAY_SIZE(qcs615_cfg),
@@ -4941,6 +5147,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id qcom_llcc_of_match[] = {
+	{ .compatible = "qcom,glymur-llcc", .data = &glymur_cfgs },
 	{ .compatible = "qcom,ipq5424-llcc", .data = &ipq5424_cfgs},
 	{ .compatible = "qcom,kaanapali-llcc", .data = &kaanapali_cfgs},
 	{ .compatible = "qcom,qcs615-llcc", .data = &qcs615_cfgs},
diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
index c52464262ab3..30b436d0140a 100644
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -74,13 +74,17 @@
 #define LLCC_CAMSRTIP      73
 #define LLCC_CAMRTRF       74
 #define LLCC_CAMSRTRF      75
+#define LLCC_OOBM_NS       81
+#define LLCC_OOBM_S        82
 #define LLCC_VIDEO_APV     83
 #define LLCC_COMPUTE1      87
 #define LLCC_CPUSS_OPP     88
 #define LLCC_CPUSSMPAM     89
+#define LLCC_VIDSC_VSP1    91
 #define LLCC_CAM_IPE_STROV 92
 #define LLCC_CAM_OFE_STROV 93
 #define LLCC_CPUSS_HEU     94
+#define LLCC_PCIE_TCU      97
 #define LLCC_MDM_PNG_FIXED 100
 
 /**

-- 
2.34.1

Re: [PATCH v2 3/3] soc: qcom: llcc-qcom: Add support for Glymur

[Konrad Dybcio]

On 11/25/25 10:16 AM, Pankaj Patil wrote:
> Add system cache table(SCT) and configs for Glymur SoC
> Updated the list of usecase id's to enable additional clients for Glymur
> 
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---

What happened to my tag? :(

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v2 3/3] soc: qcom: llcc-qcom: Add support for Glymur

[Pankaj Patil]

On 11/27/2025 3:52 PM, Konrad Dybcio wrote:
> On 11/25/25 10:16 AM, Pankaj Patil wrote:
>> Add system cache table(SCT) and configs for Glymur SoC
>> Updated the list of usecase id's to enable additional clients for Glymur
>>
>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>> ---
> What happened to my tag? :(
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
> Konrad
The commit was updated since I squashed the patch for enabling additional
usecase id's.
That makes the tag obsolete?

Re: [PATCH v2 3/3] soc: qcom: llcc-qcom: Add support for Glymur

[Konrad Dybcio]

On 11/27/25 11:37 AM, Pankaj Patil wrote:
> On 11/27/2025 3:52 PM, Konrad Dybcio wrote:
>> On 11/25/25 10:16 AM, Pankaj Patil wrote:
>>> Add system cache table(SCT) and configs for Glymur SoC
>>> Updated the list of usecase id's to enable additional clients for Glymur
>>>
>>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>>> ---
>> What happened to my tag? :(
>>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>
>> Konrad
> The commit was updated since I squashed the patch for enabling additional
> usecase id's.
> That makes the tag obsolete?

I would say it's closer to "fix a typo vs last revision" than to
"rewrite meaningful logic"

Konrad

Re: [PATCH v2 3/3] soc: qcom: llcc-qcom: Add support for Glymur

[Krzysztof Kozlowski]

On 27/11/2025 11:37, Pankaj Patil wrote:
> On 11/27/2025 3:52 PM, Konrad Dybcio wrote:
>> On 11/25/25 10:16 AM, Pankaj Patil wrote:
>>> Add system cache table(SCT) and configs for Glymur SoC
>>> Updated the list of usecase id's to enable additional clients for Glymur
>>>
>>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>>> ---
>> What happened to my tag? :(
>>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>
>> Konrad
> The commit was updated since I squashed the patch for enabling additional
> usecase id's.
> That makes the tag obsolete?

Where did you explain these reasons? Please read submitting patches
document about handling tags.

Best regards,
Krzysztof