From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E55B8C352A1 for ; Thu, 24 Nov 2022 03:45:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229823AbiKXDpw (ORCPT ); Wed, 23 Nov 2022 22:45:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229903AbiKXDpv (ORCPT ); Wed, 23 Nov 2022 22:45:51 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2F195F54; Wed, 23 Nov 2022 19:45:49 -0800 (PST) X-UUID: 6884f96fb10347dda8d5de06a59d37c6-20221124 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From:References:CC:To:Subject:MIME-Version:Date:Message-ID; bh=jrYcqp5WHNoqMyHRQ5m26zBTLl1AJjhex7T+bWp6N4w=; b=RejcPxwxe8wiOI5yKkravfIhavkhzhUlG7Tgk+VjZrd5m2SDrm/mENrRYP7aUUkjE3mPMMHUTAFuA/2sYTRR6wqTTPHWyRijPLZldiwAXl8RAA/jSQSnTMDWYiLIDpCz5RlD5bnzYEXHkXOOII4+mrvoA2LMgnloQuTczxKNM9E=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12,REQID:ed64df0c-e059-420a-86d1-806c3b30087f,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:62cd327,CLOUDID:9c4217dc-6ad4-42ff-91f3-18e0272db660,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 6884f96fb10347dda8d5de06a59d37c6-20221124 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 455475354; Thu, 24 Nov 2022 11:45:42 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 24 Nov 2022 11:45:40 +0800 Received: from [172.21.84.99] (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 24 Nov 2022 11:45:40 +0800 Message-ID: <80bc264c-7d30-574a-7b80-6cf9d40f255f@mediatek.com> Date: Thu, 24 Nov 2022 11:45:39 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH v4] arm64: dts: mt8195: Add Ethernet controller Content-Language: en-US To: Biao Huang , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: , , , , Miles Chen , Pablo Sun , Bear Wang References: <20221020085203.1974-1-biao.huang@mediatek.com> <20221020085203.1974-2-biao.huang@mediatek.com> From: Macpaul Lin In-Reply-To: <20221020085203.1974-2-biao.huang@mediatek.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 10/20/22 16:52, Biao Huang wrote: > Add Ethernet controller node for mt8195. > > Signed-off-by: Biao Huang > Reviewed-by: AngeloGioacchino Del Regno Dear Matthias, Biao also found this patch for ethernet node seems missing in 6.2 dts pull-request. Just a remind for this patch. Please help to review this patch if you have time. Thanks! > --- > arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 88 ++++++++++++++++++++ > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 86 +++++++++++++++++++ > 2 files changed, 174 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts > index 4fbd99eb496a..0e8496d837ef 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts > +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts > @@ -258,6 +258,72 @@ &mt6359_vsram_others_ldo_reg { > }; > > &pio { > + eth_default_pins: eth-default-pins { > + pins-txd { > + pinmux = , > + , > + , > + ; > + drive-strength = ; > + }; > + pins-cc { > + pinmux = , > + , > + , > + ; > + drive-strength = ; > + }; > + pins-rxd { > + pinmux = , > + , > + , > + ; > + }; > + pins-mdio { > + pinmux = , > + ; > + input-enable; > + }; > + pins-power { > + pinmux = , > + ; > + output-high; > + }; > + }; > + > + eth_sleep_pins: eth-sleep-pins { > + pins-txd { > + pinmux = , > + , > + , > + ; > + }; > + pins-cc { > + pinmux = , > + , > + , > + ; > + }; > + pins-rxd { > + pinmux = , > + , > + , > + ; > + }; > + pins-mdio { > + pinmux = , > + ; > + input-disable; > + bias-disable; > + }; > + pins-power { > + pinmux = , > + ; > + input-disable; > + bias-disable; > + }; > + }; > + > gpio_keys_pins: gpio-keys-pins { > pins { > pinmux = ; > @@ -434,6 +500,28 @@ &xhci0 { > status = "okay"; > }; > > +ð { > + phy-mode ="rgmii-rxid"; > + phy-handle = <ðernet_phy0>; > + snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>; > + snps,reset-delays-us = <0 10000 10000>; > + mediatek,tx-delay-ps = <2030>; > + pinctrl-names = "default", "sleep"; > + pinctrl-0 = <ð_default_pins>; > + pinctrl-1 = <ð_sleep_pins>; > + status = "okay"; > + > + mdio { > + compatible = "snps,dwmac-mdio"; > + #address-cells = <1>; > + #size-cells = <0>; > + ethernet_phy0: ethernet-phy@1 { > + compatible = "ethernet-phy-id001c.c916"; > + reg = <0x1>; > + }; > + }; > +}; > + > &xhci1 { > vusb33-supply = <&mt6359_vusb_ldo_reg>; > status = "okay"; > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > index 905d1a90b406..0639ad9d261c 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > @@ -1042,6 +1042,92 @@ spis1: spi@1101e000 { > status = "disabled"; > }; > > + eth: ethernet@11021000 { > + compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; > + reg = <0 0x11021000 0 0x4000>; > + interrupts = ; > + interrupt-names = "macirq"; > + clock-names = "axi", > + "apb", > + "mac_cg", > + "mac_main", > + "ptp_ref", > + "rmii_internal"; > + clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, > + <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, > + <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>, > + <&topckgen CLK_TOP_SNPS_ETH_250M>, > + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, > + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; > + assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, > + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, > + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; > + assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, > + <&topckgen CLK_TOP_ETHPLL_D8>, > + <&topckgen CLK_TOP_ETHPLL_D10>; > + power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>; > + mediatek,pericfg = <&infracfg_ao>; > + snps,axi-config = <&stmmac_axi_setup>; > + snps,mtl-rx-config = <&mtl_rx_setup>; > + snps,mtl-tx-config = <&mtl_tx_setup>; > + snps,txpbl = <16>; > + snps,rxpbl = <16>; > + snps,clk-csr = <0>; > + status = "disabled"; > + > + stmmac_axi_setup: stmmac-axi-config { > + snps,wr_osr_lmt = <0x7>; > + snps,rd_osr_lmt = <0x7>; > + snps,blen = <0 0 0 0 16 8 4>; > + }; > + > + mtl_rx_setup: rx-queues-config { > + snps,rx-queues-to-use = <4>; > + snps,rx-sched-sp; > + queue0 { > + snps,dcb-algorithm; > + snps,map-to-dma-channel = <0x0>; > + }; > + queue1 { > + snps,dcb-algorithm; > + snps,map-to-dma-channel = <0x0>; > + }; > + queue2 { > + snps,dcb-algorithm; > + snps,map-to-dma-channel = <0x0>; > + }; > + queue3 { > + snps,dcb-algorithm; > + snps,map-to-dma-channel = <0x0>; > + }; > + }; > + > + mtl_tx_setup: tx-queues-config { > + snps,tx-queues-to-use = <4>; > + snps,tx-sched-wrr; > + queue0 { > + snps,weight = <0x10>; > + snps,dcb-algorithm; > + snps,priority = <0x0>; > + }; > + queue1 { > + snps,weight = <0x11>; > + snps,dcb-algorithm; > + snps,priority = <0x1>; > + }; > + queue2 { > + snps,weight = <0x12>; > + snps,dcb-algorithm; > + snps,priority = <0x2>; > + }; > + queue3 { > + snps,weight = <0x13>; > + snps,dcb-algorithm; > + snps,priority = <0x3>; > + }; > + }; > + }; > + > xhci0: usb@11200000 { > compatible = "mediatek,mt8195-xhci", > "mediatek,mtk-xhci"; Regards, Macpaul Lin