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[83.30.147.116]) by smtp.gmail.com with ESMTPSA id w16-20020adfec50000000b003143867d2ebsm15879054wrn.63.2023.07.25.03.03.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 25 Jul 2023 03:03:06 -0700 (PDT) Message-ID: <80ce1710-38e3-2c6e-73b9-6b18c38b3ff3@gmail.com> Date: Tue, 25 Jul 2023 12:03:04 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/7] clk: qcom: hfpll: Add MSM8976 PLL data Content-Language: en-US To: Konrad Dybcio Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , AngeloGioacchino Del Regno , Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230723160827.22660-1-a39.skl@gmail.com> <20230723160827.22660-6-a39.skl@gmail.com> <411da19f-10f3-6dc1-a708-cdf06be9c4d8@linaro.org> From: Adam Skladowski In-Reply-To: <411da19f-10f3-6dc1-a708-cdf06be9c4d8@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 25.07.2023 10:02, Konrad Dybcio wrote: > On 23.07.2023 18:08, Adam Skladowski wrote: >> Add PLL configuration for MSM8976 SoC, this SoC offers 3 HFPLL. >> Small cluster offers two presets for 652-902Mhz range and 902Mhz-1.47Ghz. >> For simplicity only add second range as smaller frequencies can be obtained >> via apcs divider or safe parent this also saves us >> a hassle of reconfiguring VCO bit and config_val. >> A72 and CCI cluster only use single frequency range with their >> outputs/post_dividers/vco_bits being static. >> >> Signed-off-by: Adam Skladowski >> --- > [...] > >> +static const struct hfpll_data msm8976_a72 = { >> + .mode_reg = 0x00, >> + .l_reg = 0x04, >> + .m_reg = 0x08, >> + .n_reg = 0x0c, >> + .user_reg = 0x10, >> + .config_reg = 0x14, >> + .config_val = 0x4e0405d, >> + .status_reg = 0x1c, >> + .lock_bit = 16, >> + >> + .l_val = 0x3e, >> + .user_val = 0x100109, >> + .min_rate = 940800000UL, >> + .max_rate = 1843200000UL, > 2016000000? We are using msm kernel as base not SODP ports. https://android.googlesource.com/kernel/msm/+/android-lego-6.0.1_r0.2/drivers/clk/qcom/clock-cpu-8976.c https://android.googlesource.com/kernel/msm.git/+/android-msm-lego-3.10-marshmallow-dr/arch/arm/boot/dts/qcom/msm8976.dtsi#349 > [...] >> static const struct of_device_id qcom_hfpll_match_table[] = { >> { .compatible = "qcom,hfpll", &hdata }, >> + { .compatible = "qcom,msm8976-hfpll-a53", &msm8976_a53 }, >> + { .compatible = "qcom,msm8976-hfpll-a72", &msm8976_a72 }, >> + { .compatible = "qcom,msm8976-hfpll-cci", &msm8976_cci }, > .data = is missing > > Konrad Seems like i took "inspiration" from also not great code, albeit it does work somehow when printing inside init, will fix in v3 Thanks Angelo/Konrad