From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Chen Wang <unicornxw@gmail.com>,
aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org,
krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
palmer@dabbelt.com, paul.walmsley@sifive.com,
richardcochran@gmail.com, robh+dt@kernel.org, sboyd@kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com,
guoren@kernel.org, jszhang@kernel.org, inochiama@outlook.com,
samuel.holland@sifive.com
Cc: Chen Wang <unicorn_wang@outlook.com>
Subject: Re: [PATCH v2 3/4] clk: sophgo: Add SG2042 clock generator driver
Date: Mon, 27 Nov 2023 08:12:00 +0100 [thread overview]
Message-ID: <81d421c8-bfd6-42b5-9da1-f067792f8f48@linaro.org> (raw)
In-Reply-To: <c06130afb4bdc1890b4e8d29388fa6feef1f1826.1701044106.git.unicorn_wang@outlook.com>
On 27/11/2023 02:15, Chen Wang wrote:
> From: Chen Wang <unicorn_wang@outlook.com>
>
> Add a driver for the SOPHGO SG2042 clock generator.
>
> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
...
> +static void __init sg2042_clk_init(struct device_node *node)
> +{
> + struct sg2042_clk_data *clk_data = NULL;
> + int i, ret = 0;
> + int num_clks = 0;
> +
> + num_clks = ARRAY_SIZE(sg2042_pll_clks) +
> + ARRAY_SIZE(sg2042_div_clks) +
> + ARRAY_SIZE(sg2042_gate_clks) +
> + ARRAY_SIZE(sg2042_mux_clks);
> + if (num_clks == 0) {
> + ret = -EINVAL;
> + goto error_out;
> + }
> +
> + ret = sg2042_clk_init_clk_data(node, num_clks, &clk_data);
> + if (ret < 0)
> + goto error_out;
> +
> + ret = sg2042_clk_register_plls(clk_data, sg2042_pll_clks,
> + ARRAY_SIZE(sg2042_pll_clks));
> + if (ret)
> + goto cleanup;
> +
> + ret = sg2042_clk_register_divs(clk_data, sg2042_div_clks,
> + ARRAY_SIZE(sg2042_div_clks));
> + if (ret)
> + goto cleanup;
> +
> + ret = sg2042_clk_register_gates(clk_data, sg2042_gate_clks,
> + ARRAY_SIZE(sg2042_gate_clks));
> + if (ret)
> + goto cleanup;
> +
> + ret = sg2042_clk_register_muxs(clk_data, sg2042_mux_clks,
> + ARRAY_SIZE(sg2042_mux_clks));
> + if (ret)
> + goto cleanup;
> +
> + for (i = 0; i < num_clks; i++)
> + dbg_info("provider [%d]: %s\n", i, clk_hw_get_name(clk_data->onecell_data.hws[i]));
> + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, &clk_data->onecell_data);
> + if (ret)
> + goto cleanup;
> +
> + return;
> +
> +cleanup:
> + for (i = 0; i < num_clks; i++) {
> + if (clk_data->onecell_data.hws[i] != NULL)
> + clk_hw_unregister(clk_data->onecell_data.hws[i]);
> + }
> + kfree(clk_data);
> +
> +error_out:
> + pr_err("%s failed error number %d\n", __func__, ret);
> +}
> +
> +CLK_OF_DECLARE(sg2042_clk, "sophgo,sg2042-clkgen", sg2042_clk_init);
No, this should be platform device. It's a child of another device, so
you cannot use other way of init ordering.
> diff --git a/drivers/clk/sophgo/clk-sophgo-sg2042.h b/drivers/clk/sophgo/clk-sophgo-sg2042.h
> new file mode 100644
> index 000000000000..ca1c8b9a937a
> --- /dev/null
...
> +#define to_sg2042_mux_nb(_nb) container_of(_nb, struct sg2042_mux_clock, clk_nb)
> +
> +#ifdef DEBUG
> + #define dbg_info(format, arg...) \
> + pr_info("--> %s: "format"", __func__, ## arg)
> +#else
> + #define dbg_info(format, arg...)
> +#endif
Drop custom debug prints.
> +
> +#endif /* __CLK_SOPHGO_SG2042_H */
Best regards,
Krzysztof
next prev parent reply other threads:[~2023-11-27 7:12 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-27 0:57 [PATCH v2 0/4] riscv: sophgo: add clock support for sg2042 Chen Wang
2023-11-27 0:58 ` [PATCH v2 1/4] dt-bindings: clock: sophgo: Add SG2042 bindings Chen Wang
2023-11-27 7:08 ` Krzysztof Kozlowski
2023-11-27 0:58 ` [PATCH v2 2/4] dt-bindings: soc: sophgo: Add Sophgo syscon module Chen Wang
2023-11-27 7:09 ` Krzysztof Kozlowski
2023-11-27 1:15 ` [PATCH v2 3/4] clk: sophgo: Add SG2042 clock generator driver Chen Wang
2023-11-27 7:12 ` Krzysztof Kozlowski [this message]
2023-11-27 8:07 ` Chen Wang
2023-11-27 9:16 ` Krzysztof Kozlowski
2023-11-30 6:37 ` Chen Wang
2023-11-30 8:01 ` Krzysztof Kozlowski
2023-11-30 11:42 ` Chen Wang
2023-11-30 8:12 ` Conor Dooley
2023-11-30 11:32 ` Chen Wang
2023-11-27 1:16 ` [PATCH v2 4/4] riscv: dts: add clock generator for Sophgo SG2042 SoC Chen Wang
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