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From: Tudor Ambarus <tudor.ambarus@linaro.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
	Geert Uytterhoeven <geert@linux-m68k.org>
Cc: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org,
	semen.protsenko@linaro.org, alim.akhtar@samsung.com,
	linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, andre.draszik@linaro.org,
	peter.griffin@linaro.org, kernel-team@android.com,
	willmcvicker@google.com, conor+dt@kernel.org,
	devicetree@vger.kernel.org, arnd@arndb.de,
	Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	Wolfram Sang <wsa+renesas@sang-engineering.com>
Subject: Re: [PATCH 01/12] spi: dt-bindings: introduce the ``fifo-depth`` property
Date: Mon, 12 Feb 2024 06:17:14 +0000	[thread overview]
Message-ID: <828d9947-ee96-4c2f-b856-0fac3640c863@linaro.org> (raw)
In-Reply-To: <be84e32e-e11d-47fe-ad56-da8b0dec5007@linaro.org>



Hi, Geert, Krzysztof,

On 2/11/24 13:49, Krzysztof Kozlowski wrote:> On 09/02/2024 18:13, Geert
Uytterhoeven wrote:
>> Hi Tudor,
>>
>> On Thu, Feb 8, 2024 at 2:51 PM Tudor Ambarus <tudor.ambarus@linaro.org> wrote:
>>> There are instances of the same IP that are configured by the integrator
>>> with different FIFO depths. Introduce the fifo-depth property to allow
>>> such nodes to specify their FIFO depth.
>>>
>>> We haven't seen SPI IPs with different FIFO depths for RX and TX, thus
>>> introduce a single property.
>>
>> Ha...
>>
>> Current documentation for the Clock-Synchronized Serial Interface with
>> FIFO (MSIOF) on e.g. R-Car Gen2 and later states:
>>
>>     FIFO capacity: 32 bits × 64 stages for transmission and 32 bits ×
>> 256 stages for reception
>>
>> Initially (many years ago), there was some doubt about the validity
>> of these values (older variants on SH supported 64/64), hence
>> drivers/spi/spi-sh-msiof.c still has
>>
>>     .tx_fifo_size = 64,
>>     .rx_fifo_size = 64,
>>
>> Probably we should test and revisit this...
>>
>>> --- a/Documentation/devicetree/bindings/spi/spi-controller.yaml
>>> +++ b/Documentation/devicetree/bindings/spi/spi-controller.yaml
>>> @@ -69,6 +69,11 @@ properties:
>>>           Should be generally avoided and be replaced by
>>>           spi-cs-high + ACTIVE_HIGH.
>>>
>>> +  fifo-depth:
>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>> +    description:
>>> +      Size of the data FIFO in bytes.
>>
>> I think it is prudent to consider the asymmetric case, too.
>> Whether that should be just two properties ("rx-fifo-depth" and
>> "tx-fifo-depth"), or also a third "fifo-depth", I defer to the DT
>> maintainers...

Thanks, Geert for the insight!
> 
> Since most of the cases FIFO depth tx=rx, we could go with three
> properties and:
> 
> allOf:
>  - not:
>      required:
>        - fifo-depth
>        - tx-fifo-depth
>  - not:
>      required:
>        - fifo-depth
>        - rx-fifo-depth
> 
> and probably dependencies between rx and tx (see example-schema).
> 
Great. Thanks, Krzysztof! I'll give it a try.
Cheers,
ta

  reply	other threads:[~2024-02-12  6:17 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-08 13:50 [PATCH 00/12] spi: s3c64xx: remove OF alias ID dependency Tudor Ambarus
2024-02-08 13:50 ` [PATCH 01/12] spi: dt-bindings: introduce the ``fifo-depth`` property Tudor Ambarus
2024-02-08 18:24   ` Conor Dooley
2024-02-09 13:56     ` Tudor Ambarus
2024-02-09 16:21       ` Conor Dooley
2024-02-09 16:55         ` Tudor Ambarus
2024-02-12 10:38           ` Geert Uytterhoeven
2024-02-12 12:01             ` Tudor Ambarus
2024-02-09 17:41         ` Mark Brown
2024-02-09 17:13   ` Geert Uytterhoeven
2024-02-11 13:49     ` Krzysztof Kozlowski
2024-02-12  6:17       ` Tudor Ambarus [this message]
2024-02-08 13:50 ` [PATCH 02/12] spi: s3c64xx: define a magic value Tudor Ambarus
2024-02-08 13:50 ` [PATCH 03/12] spi: s3c64xx: allow full FIFO masks Tudor Ambarus
2024-02-08 13:50 ` [PATCH 04/12] spi: s3c64xx: determine the fifo depth only once Tudor Ambarus
2024-02-08 13:50 ` [PATCH 05/12] spi: s3c64xx: retrieve the FIFO depth from the device tree Tudor Ambarus
2024-02-08 13:50 ` [PATCH 06/12] spi: s3c64xx: allow FIFO depth to be determined from the compatible Tudor Ambarus
2024-02-08 13:50 ` [PATCH 07/12] spi: s3c64xx: let the SPI core determine the bus number Tudor Ambarus
2024-02-08 13:50 ` [PATCH 08/12] spi: s3c64xx: introduce s3c64xx_spi_set_port_id() Tudor Ambarus
2024-02-08 13:50 ` [PATCH 09/12] spi: s3c64xx: get rid of the OF alias ID dependency Tudor Ambarus
2024-02-08 13:50 ` [PATCH 10/12] spi: s3c64xx: deprecate fifo_lvl_mask, rx_lvl_offset and port_id Tudor Ambarus
2024-02-08 13:50 ` [PATCH 11/12] spi: s3c64xx: switch gs101 to new port config data Tudor Ambarus
2024-02-08 16:01   ` Tudor Ambarus
2024-02-08 13:50 ` [PATCH 12/12] spi: s3c64xx: switch exynos850 " Tudor Ambarus

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