From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Yu Tu <yu.tu@amlogic.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
Neil Armstrong <narmstrong@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Kevin Hilman <khilman@baylibre.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Subject: Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings
Date: Thu, 28 Jul 2022 10:41:03 +0200 [thread overview]
Message-ID: <82e3fd36-df96-a555-4cea-47fabd26502b@linaro.org> (raw)
In-Reply-To: <20220728054202.6981-2-yu.tu@amlogic.com>
On 28/07/2022 07:42, Yu Tu wrote:
> Add new clock controller compatible and dt-bindings header for the
> Everything-Else domain of the S4 SoC.
>
> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index c1abc53f9e91..f872d0c0c253 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1775,6 +1775,7 @@ F: Documentation/devicetree/bindings/clock/amlogic*
> F: drivers/clk/meson/
> F: include/dt-bindings/clock/gxbb*
> F: include/dt-bindings/clock/meson*
> +F: include/dt-bindings/clock/s4-clkc.h
>
> ARM/Amlogic Meson SoC Crypto Drivers
> M: Corentin Labbe <clabbe@baylibre.com>
> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
> new file mode 100644
> index 000000000000..b686c8877419
> --- /dev/null
> +++ b/include/dt-bindings/clock/s4-clkc.h
Filename with vendor prefix, so:
amlogic,s4-clkc.h
> @@ -0,0 +1,146 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
> + * Author: Yu Tu <yu.tu@amlogic.com>
> + */
> +
> +#ifndef _DT_BINDINGS_CLOCK_S4_CLKC_H
> +#define _DT_BINDINGS_CLOCK_S4_CLKC_H
> +
> +/*
> + * CLKID index values
> + */
> +
> +#define CLKID_FIXED_PLL 1
> +#define CLKID_FCLK_DIV2 3
> +#define CLKID_FCLK_DIV3 5
> +#define CLKID_FCLK_DIV4 7
> +#define CLKID_FCLK_DIV5 9
> +#define CLKID_FCLK_DIV7 11
Why these aren't continuous? IDs are expected to be incremented by 1.
> +
> +#endif /* _DT_BINDINGS_CLOCK_S4_CLKC_H */
Best regards,
Krzysztof
next prev parent reply other threads:[~2022-07-28 8:41 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-28 5:41 [PATCH V2 0/3] Add S4 SoC clock controller driver Yu Tu
2022-07-28 5:42 ` [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings Yu Tu
2022-07-28 8:41 ` Krzysztof Kozlowski [this message]
2022-07-28 8:50 ` Jerome Brunet
2022-07-28 9:02 ` Krzysztof Kozlowski
2022-07-28 9:09 ` Jerome Brunet
2022-07-28 9:48 ` Krzysztof Kozlowski
2022-07-28 9:54 ` Jerome Brunet
2022-07-28 10:07 ` Krzysztof Kozlowski
2022-07-28 10:05 ` Yu Tu
2022-07-28 10:09 ` Krzysztof Kozlowski
2022-07-28 10:19 ` Yu Tu
2022-07-28 11:48 ` Jerome Brunet
2022-07-29 5:51 ` Yu Tu
2022-07-28 5:42 ` [PATCH V2 2/3] arm64: dts: meson: add S4 Soc clock controller in DT Yu Tu
2022-07-28 5:42 ` [PATCH V2 3/3] clk: meson: s4: add s4 SoC clock controller driver Yu Tu
2022-07-28 7:08 ` [PATCH V2 0/3] Add S4 " Jerome Brunet
2022-07-28 8:06 ` Yu Tu
2022-07-28 8:14 ` Yu Tu
2022-07-28 8:27 ` Jerome Brunet
2022-07-28 8:55 ` Yu Tu
2022-07-28 9:03 ` Jerome Brunet
2022-07-28 9:52 ` Yu Tu
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