From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7289C004D4 for ; Thu, 19 Jan 2023 12:34:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230344AbjASMe1 (ORCPT ); Thu, 19 Jan 2023 07:34:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230467AbjASMeE (ORCPT ); Thu, 19 Jan 2023 07:34:04 -0500 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F25677ED4C for ; Thu, 19 Jan 2023 04:30:08 -0800 (PST) Received: by mail-wm1-x32d.google.com with SMTP id j17so1421808wms.0 for ; Thu, 19 Jan 2023 04:30:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=UcNbpiHNkJaSlONNLaq69/U1cHe0Wi/deeXgruiIYlk=; b=zs1r3iTSdsastCcqC1s6jGo+TMaT++Dj/p0LpEv0Rc68YNsHs7a66i3FWNetl7mOk6 7IGujmpIUkdMotwpYTQOKI1Kic2VCZirLmVFHBV4uRLf7LjYLdHEyz8T2kaOQYYv5cnV 7jVZSc8xv7W5mwt9QOysf+VPkuLuvpFDy9beQUDRUaXqcPO6JvIsOFbjkT/XUxsV14pU 9P8yt4rmJkY5FTONzvTx3SdklJU2g1RcyaC5YG9DFSywVMTzpdj9epxAIGadnaEJr8sN 16R/XWnbnjRjWIQ55vUnxX81Pwipdi/7ARLnltxEc4LfOAaEhfZMmIhdH5VvjBScH/P3 SRdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=UcNbpiHNkJaSlONNLaq69/U1cHe0Wi/deeXgruiIYlk=; b=ifb5s1K3WDWKoZiA7bRS5lSKGBHaWuW9wBuekvqPbxdU9iqS0vlVrJu04GcOWpvWSt ZB8wrfyX6CHwt+rFs0b6TeCNN11ipaHrRxIcLVkyyrwusjl0DxqlI/rf0ILkZNvFLf/1 uUS7t8EaBvatD+74VhTY58mCTZ8ijCJj9j8d/7FMCj9ipt1QMsqoYbMnJmVYlQVXzAFx jEWl/euQljAyrWq+HxaUUUD4yLGxI6bgF6ZkxwIwicRz+Kqr96WoOcWvDUhO5UIFqI+r TH9Jn7jFXeODXTxIEeOGSHaePJZ3mE6MKEpBz8RQ2t2mYA0n+Y6bdtWcPcGZvpl6K3vq zcdA== X-Gm-Message-State: AFqh2kri2MuRSBhT3xIX5n2uGzBFyA6TxL57ACETpn8ges7ARzyEJnhE +XTM4F508hdzi8bjZ+eMq3Yw7g== X-Google-Smtp-Source: AMrXdXvOzeYIEi4dp0Tgez1Sr/c2pgde4bny/gVuIgmZz8MDwKTiqF6jrgaPfXhhhJWF/xIm33wYIg== X-Received: by 2002:a05:600c:1d22:b0:3d9:6bc3:b8b9 with SMTP id l34-20020a05600c1d2200b003d96bc3b8b9mr10165519wms.9.1674131380376; Thu, 19 Jan 2023 04:29:40 -0800 (PST) Received: from [192.168.1.109] ([178.197.216.144]) by smtp.gmail.com with ESMTPSA id ay13-20020a05600c1e0d00b003cf71b1f66csm5119821wmb.0.2023.01.19.04.29.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Jan 2023 04:29:39 -0800 (PST) Message-ID: <8322af81-139c-b840-dbf0-d52d86e92032@linaro.org> Date: Thu, 19 Jan 2023 13:29:38 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.0 Subject: Re: [PATCH v2 0/2] arm64: dts: qcom: sm8550: Add PCIe HC and PHY support Content-Language: en-US To: Abel Vesa , Johan Hovold Cc: Bjorn Andersson , Rob Herring , Konrad Dybcio , Andy Gross , Krzysztof Kozlowski , devicetree@vger.kernel.org, Linux Kernel Mailing List , linux-arm-msm@vger.kernel.org References: <20230118230526.1499328-1-abel.vesa@linaro.org> <167408614065.2989059.2950818972854332656.b4-ty@kernel.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 19/01/2023 13:09, Abel Vesa wrote: > On 23-01-19 08:33:20, Johan Hovold wrote: >> On Wed, Jan 18, 2023 at 05:55:31PM -0600, Bjorn Andersson wrote: >>> On Thu, 19 Jan 2023 01:05:24 +0200, Abel Vesa wrote: >>>> This patchset adds PCIe controllers and PHYs support to SM8550 platform >>>> and enables them on the MTP board. >>>> >>>> The v1 was here: >>>> https://lore.kernel.org/all/20221116130430.2812173-1-abel.vesa@linaro.org/ >>>> >>>> Changes since v1: >>>> * ordered pcie related nodes alphabetically in MTP dts >>>> * dropped the pipe_mux, phy_pipe and ref clocks from the pcie nodes >>>> * dropped the child node from the phy nodes, like Johan suggested, >>>> and updated to use the sc8280xp binding scheme >>>> * changed "pcie_1_nocsr_com_phy_reset" 2nd reset name of pcie1_phy >>>> to "nocsr" >>>> * reordered all pcie nodes properties to look similar to the ones >>>> from sc8280xp >>>> >>>> [...] >>> >>> Applied, thanks! >>> >>> [1/2] arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes >>> commit: 7d1158c984d37e79ab8bb55ab152a0b35566cb89 >>> [2/2] arm64: dts: qcom: sm8550-mtp: Add PCIe PHYs and controllers nodes >>> commit: 1eeef306b5d80494cdb149f058013c3ab43984b4 >> >> I believe there were still some changes needed to the controller >> and PHY bindings so this should not have been merged. >> >> https://lore.kernel.org/all/Y8fuUI4xaNkADkWl@hovoldconsulting.com/ >> https://lore.kernel.org/lkml/Y8giHJMtPu4wTlmA@hovoldconsulting.com/ >> >> Perhaps in the future you can send the dts changes along with the (PHY) >> driver changes so that they can be kept in lock-step and avoid this. > > Well, that is a bit hard to do, because phy patches are based on > linux-phy/next, while dtsi patches are based on Bjorn's tree which, > so ... ... which we long time solved by basing your patches on linux-next. That's the only way for inter-tree patchsets to be properly based. Best regards, Krzysztof