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[109.252.136.171]) by smtp.googlemail.com with ESMTPSA id b11-20020ac2410b000000b004457116a575sm1325583lfi.273.2022.03.19.08.42.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 19 Mar 2022 08:42:29 -0700 (PDT) Message-ID: <83bc4c12-13e3-d239-3845-a3541b1fbb2a@gmail.com> Date: Sat, 19 Mar 2022 18:42:28 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [Patch v5 1/4] memory: tegra: Add memory controller channels support Content-Language: en-US To: Ashish Mhetre , krzysztof.kozlowski@canonical.com, robh+dt@kernel.org, thierry.reding@gmail.com, jonathanh@nvidia.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Cc: vdumpa@nvidia.com, Snikam@nvidia.com References: <20220316092525.4554-1-amhetre@nvidia.com> <20220316092525.4554-2-amhetre@nvidia.com> From: Dmitry Osipenko In-Reply-To: <20220316092525.4554-2-amhetre@nvidia.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org 16.03.2022 12:25, Ashish Mhetre пишет: > From tegra186 onwards, memory controller support multiple channels. > Add support for mapping address spaces of these channels. > Make sure that number of channels are as expected on each SOC. > During error interrupts from memory controller, appropriate registers > from these channels need to be accessed for logging error info. > > Signed-off-by: Ashish Mhetre > --- > drivers/memory/tegra/mc.c | 6 ++++ > drivers/memory/tegra/tegra186.c | 52 +++++++++++++++++++++++++++++++++ > drivers/memory/tegra/tegra194.c | 1 + > drivers/memory/tegra/tegra234.c | 1 + > include/soc/tegra/mc.h | 7 +++++ > 5 files changed, 67 insertions(+) > > diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c > index bf3abb6d8354..3cda1d9ad32a 100644 > --- a/drivers/memory/tegra/mc.c > +++ b/drivers/memory/tegra/mc.c > @@ -749,6 +749,12 @@ static int tegra_mc_probe(struct platform_device *pdev) > if (IS_ERR(mc->regs)) > return PTR_ERR(mc->regs); > > + if (mc->soc->ops && mc->soc->ops->map_regs) { > + err = mc->soc->ops->map_regs(mc, pdev); > + if (err < 0) > + return err; > + } > + > mc->debugfs.root = debugfs_create_dir("mc", NULL); > > if (mc->soc->ops && mc->soc->ops->probe) { > diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c > index 3d153881abc1..a8a45e6ff1f1 100644 > --- a/drivers/memory/tegra/tegra186.c > +++ b/drivers/memory/tegra/tegra186.c > @@ -139,11 +139,62 @@ static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev) > return 0; > } > > +static int tegra186_mc_map_regs(struct tegra_mc *mc, > + struct platform_device *pdev) > +{ > + struct device_node *np = pdev->dev.parent->of_node; > + int num_dt_channels, reg_cells = 0; > + struct resource *res; > + int i, ret; > + u32 val; > + > + ret = of_property_read_u32(np, "#address-cells", &val); > + if (ret) { > + dev_err(&pdev->dev, "missing #address-cells property\n"); > + return ret; > + } > + > + reg_cells = val; > + > + ret = of_property_read_u32(np, "#size-cells", &val); > + if (ret) { > + dev_err(&pdev->dev, "missing #size-cells property\n"); > + return ret; > + } > + > + reg_cells += val; > + > + num_dt_channels = of_property_count_elems_of_size(pdev->dev.of_node, "reg", > + reg_cells * sizeof(u32)); > + /* > + * On tegra186 onwards, memory controller support multiple channels. > + * Apart from regular memory controller channels, there is one broadcast > + * channel and one for stream-id registers. > + */ > + if (num_dt_channels < mc->soc->num_channels + 2) { > + dev_warn(&pdev->dev, "MC channels are missing, please update\n"); Update what? > + return 0; > + } > + > + mc->mcb_regs = devm_platform_get_and_ioremap_resource(pdev, 1, &res); Can't we name each reg bank individually in the DT and then use devm_platform_ioremap_resource_byname()? ... > @@ -212,6 +217,8 @@ struct tegra_mc { > struct tegra_smmu *smmu; > struct gart_device *gart; > void __iomem *regs; > + void __iomem *mcb_regs; > + void __iomem *mc_regs[MC_MAX_CHANNELS]; s/mc_regs/ch_regs/ ?