From: Wenjia Zhang <wenjia.zhang@oss.qualcomm.com>
To: Harshal Dev <harshal.dev@oss.qualcomm.com>,
Thara Gopinath <thara.gopinath@gmail.com>,
Herbert Xu <herbert@gondor.apana.org.au>,
"David S. Miller" <davem@davemloft.net>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Cc: Neeraj Soni <neeraj.soni@oss.qualcomm.com>,
Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>,
Abel Vesa <abel.vesa@oss.qualcomm.com>,
linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/2] arm64: dts: qcom: glymur: Add crypto engine and BAM
Date: Tue, 12 May 2026 16:04:21 +0800 [thread overview]
Message-ID: <83c260b9-dd7f-4c28-ab83-91853afa08a0@oss.qualcomm.com> (raw)
In-Reply-To: <20260505-glymur_crypto_enablement-v2-2-bf115aeb1459@oss.qualcomm.com>
On 5/5/2026 3:40 PM, Harshal Dev wrote:
> On almost all Qualcomm platforms, including Glymur, there is a Crypto
> engine IP block to which the CPU can off-load cryptographic computations
> for achieving acceleration.
> The engine is also DMA capable due to the presence of an associated Bus
> Access Manager (BAM) module.
>
> Describe the Crypto engine and its BAM.
>
> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur.dtsi | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index f23cf81ddb77..349da9966d52 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -3675,6 +3675,32 @@ pcie3b_phy: phy@f10000 {
> status = "disabled";
> };
>
> + cryptobam: dma-controller@1dc4000 {
> + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
> + reg = <0x0 0x01dc4000 0x0 0x28000>;
> + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
> + #dma-cells = <1>;
> + iommus = <&apps_smmu 0x80 0x0>,
> + <&apps_smmu 0x81 0x0>;
> + qcom,ee = <0>;
> + qcom,controlled-remotely;
> + num-channels = <20>;
> + qcom,num-ees = <4>;
> + };
> +
> + crypto: crypto@1dfa000 {
> + compatible = "qcom,glymur-qce", "qcom,sm8150-qce", "qcom,qce";
> + reg = <0x0 0x01dfa000 0x0 0x6000>;
> + dmas = <&cryptobam 4>, <&cryptobam 5>;
> + dma-names = "rx",
> + "tx";
> + iommus = <&apps_smmu 0x80 0x0>,
> + <&apps_smmu 0x81 0x0>;
> + interconnects = <&aggre1_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "memory";
> + };
> +
> tcsr_mutex: hwlock@1f40000 {
> compatible = "qcom,tcsr-mutex";
> reg = <0x0 0x01f40000 0x0 0x20000>;
Tested-by: Wenjia Zhang <wenjia.zhang@oss.qualcomm.com> # on Glymur-crd
device
root@qcom-armv8a:~# bash /usr/libexec/libkcapi/kcapi-convenience.sh
[PASSED: 64-bit - 7.0.0-next-20260415-00003-g5de0c764975a-dirty]
Convenience message digest operation
===================================================================
Number of failures: 0
root@qcom-armv8a:~#
Regards,
Wenjia
next prev parent reply other threads:[~2026-05-12 8:04 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-05 7:40 [PATCH v2 0/2] Add Crypto Engine support for the Glymur SoC Harshal Dev
2026-05-05 7:40 ` [PATCH v2 1/2] dt-bindings: crypto: qcom-qce: Document the Glymur crypto engine Harshal Dev
2026-05-05 7:40 ` [PATCH v2 2/2] arm64: dts: qcom: glymur: Add crypto engine and BAM Harshal Dev
2026-05-12 8:04 ` Wenjia Zhang [this message]
2026-05-12 20:22 ` (subset) [PATCH v2 0/2] Add Crypto Engine support for the Glymur SoC Bjorn Andersson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=83c260b9-dd7f-4c28-ab83-91853afa08a0@oss.qualcomm.com \
--to=wenjia.zhang@oss.qualcomm.com \
--cc=abel.vesa@oss.qualcomm.com \
--cc=andersson@kernel.org \
--cc=conor+dt@kernel.org \
--cc=davem@davemloft.net \
--cc=devicetree@vger.kernel.org \
--cc=dmitry.baryshkov@oss.qualcomm.com \
--cc=harshal.dev@oss.qualcomm.com \
--cc=herbert@gondor.apana.org.au \
--cc=konradybcio@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=kuldeep.singh@oss.qualcomm.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-crypto@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=neeraj.soni@oss.qualcomm.com \
--cc=robh@kernel.org \
--cc=thara.gopinath@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox