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([2a02:810d:15c0:828:62f5:eb43:f726:5fee]) by smtp.gmail.com with ESMTPSA id xg12-20020a170907320c00b0094ee99eeb01sm7389793ejb.150.2023.04.19.00.51.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 19 Apr 2023 00:51:49 -0700 (PDT) Message-ID: <83c8bce1-f4e2-899e-46a9-0ba9da702572@linaro.org> Date: Wed, 19 Apr 2023 09:51:48 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v3 4/5] arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node Content-Language: en-US To: Jayesh Choudhary , nm@ti.com, vigneshr@ti.com, afd@ti.com Cc: s-vadapalli@ti.com, kristo@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, a-bhatia1@ti.com References: <20230419061710.290068-1-j-choudhary@ti.com> <20230419061710.290068-5-j-choudhary@ti.com> From: Krzysztof Kozlowski In-Reply-To: <20230419061710.290068-5-j-choudhary@ti.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 19/04/2023 08:17, Jayesh Choudhary wrote: > From: Rahul T R > > Add DSS and DP-bridge node for J784S4 SoC. DSS IP in J784S4 is > same as DSS IP in J721E, so same compatible is being used. > The DP is Cadence MHDP8546. > > Signed-off-by: Rahul T R > [j-choudhary@ti.com: move all k3-j784s4-main.dtsi changes together] > Signed-off-by: Jayesh Choudhary > --- > arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 77 ++++++++++++++++++++++ > 1 file changed, 77 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > index 51aa476dedba..739741e93bc1 100644 > --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > @@ -1373,4 +1373,81 @@ main_spi7: spi@2170000 { > clocks = <&k3_clks 383 1>; > status = "disabled"; > }; > + > + mhdp: dp-bridge@a000000 { > + compatible = "ti,j721e-mhdp8546"; > + > + reg = <0x0 0xa000000 0x0 0x30a00>, > + <0x0 0x4f40000 0x0 0x20>; > + reg-names = "mhdptx", "j721e-intg"; > + > + clocks = <&k3_clks 217 11>; > + > + interrupt-parent = <&gic500>; > + interrupts = ; > + > + power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; > + > + status = "disabled"; > + > + dp0_ports: ports { > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > + dss: dss@4a00000 { > + compatible = "ti,j721e-dss"; > + reg = > + <0x00 0x04a00000 0x00 0x10000>, Fix indent/stray line break. > + <0x00 0x04a10000 0x00 0x10000>, > + <0x00 0x04b00000 0x00 0x10000>, > + <0x00 0x04b10000 0x00 0x10000>, > + > + <0x00 0x04a20000 0x00 0x10000>, > + <0x00 0x04a30000 0x00 0x10000>, > + <0x00 0x04a50000 0x00 0x10000>, > + <0x00 0x04a60000 0x00 0x10000>, > + > + <0x00 0x04a70000 0x00 0x10000>, > + <0x00 0x04a90000 0x00 0x10000>, > + <0x00 0x04ab0000 0x00 0x10000>, > + <0x00 0x04ad0000 0x00 0x10000>, > + > + <0x00 0x04a80000 0x00 0x10000>, > + <0x00 0x04aa0000 0x00 0x10000>, > + <0x00 0x04ac0000 0x00 0x10000>, > + <0x00 0x04ae0000 0x00 0x10000>, > + <0x00 0x04af0000 0x00 0x10000>; > + > + reg-names = "common_m", "common_s0", > + "common_s1", "common_s2", > + "vidl1", "vidl2","vid1","vid2", > + "ovr1", "ovr2", "ovr3", "ovr4", > + "vp1", "vp2", "vp3", "vp4", > + "wb"; > + > + clocks = <&k3_clks 218 0>, Broken indentation. Best regards, Krzysztof