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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2698016bea0sm148159875ad.40.2025.09.22.20.48.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 22 Sep 2025 20:48:38 -0700 (PDT) Message-ID: <83e8c8b6-fd2c-41f5-8732-703d47764d0f@oss.qualcomm.com> Date: Tue, 23 Sep 2025 11:48:31 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 12/14] phy: qcom: qmp-usbc: Add QCS615 USB/DP PHY config and DP mode support To: Dmitry Baryshkov Cc: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, fange.zhang@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, li.liu@oss.qualcomm.com, Bjorn Andersson , Konrad Dybcio References: <20250919-add-displayport-support-for-qcs615-platform-v5-0-eae6681f4002@oss.qualcomm.com> <20250919-add-displayport-support-for-qcs615-platform-v5-12-eae6681f4002@oss.qualcomm.com> <14cdf3a4-714c-4136-8c1d-99392e7911f5@oss.qualcomm.com> <2ewxoe76rrii4w3n5b6wl32vmatcp2boj75o65cuq5nx4f2a55@7cn6m7oxzu6c> <28eef277-c778-4ffe-94c6-2e90d58633de@oss.qualcomm.com> From: Xiangxu Yin In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: mjTWilM7kKNkTTtSUuNukg5WVzNGE0sO X-Authority-Analysis: v=2.4 cv=Pc//hjhd c=1 sm=1 tr=0 ts=68d21898 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=NbDaqmtucRuFR4rafzwA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: mjTWilM7kKNkTTtSUuNukg5WVzNGE0sO X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTIzMDAyMCBTYWx0ZWRfX4Mwf3wDCR28G h3TiBKwajZzRDNip0Sax/LBOCYjHXapE4gHE90Ic9Ci2EGoOM6ntb9FbWNBgMPNJcj7wLsfCp9J gXTYDbW4B+Nv6BsphuX9YaMHDJQWX8WBVKz9qUyYHh6v/udMdj1IPsvaiGT6H731Hevu140JH4k uIyoqhyo8wsrZQ2PgjQ9/vK36l3ErVqDBQbMMvv+4/rb5PsGCdwoY+1T0UE9gE8eyRzJE51ATR7 He/12hVCvGcPLiwExje7SwaDBnKE2wQX/wK2zeVkIg7LLsF/JC0dKwSMYtRZt3kEHGbD+3NYPDd i+c0z/r61FgEQqWr949p4+CcdGq7CBvoMi7lCsokg7mz07KmMMAB5WL7oegaT/+y50LHtdZ1fRf 4VWsZ2mG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-23_01,2025-09-22_05,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 bulkscore=0 malwarescore=0 impostorscore=0 spamscore=0 suspectscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509230020 On 9/23/2025 7:38 AM, Dmitry Baryshkov wrote: > On Mon, Sep 22, 2025 at 07:28:17PM +0800, Xiangxu Yin wrote: >> On 9/22/2025 5:45 PM, Dmitry Baryshkov wrote: >>> On Mon, Sep 22, 2025 at 02:58:17PM +0800, Xiangxu Yin wrote: >>>> On 9/20/2025 2:41 AM, Dmitry Baryshkov wrote: >>>>> On Fri, Sep 19, 2025 at 10:24:29PM +0800, Xiangxu Yin wrote: >>>>>> Add QCS615-specific configuration for USB/DP PHY, including DP init >>>>>> routines, voltage swing tables, and platform data. Add compatible >>>>>> "qcs615-qmp-usb3-dp-phy". >>>>>> >>>>>> Signed-off-by: Xiangxu Yin >>>>>> --- >>>>>> drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 395 +++++++++++++++++++++++++++++++ >>>>>> 1 file changed, 395 insertions(+) >>>>>> >>>>>> + >>>>>> + writel(0x3f, qmp->dp_tx + QSERDES_V2_TX_TRANSCEIVER_BIAS_EN); >>>>>> + writel(0x10, qmp->dp_tx + QSERDES_V2_TX_HIGHZ_DRVR_EN); >>>>>> + writel(0x0a, qmp->dp_tx + QSERDES_V2_TX_TX_POL_INV); >>>>>> + writel(0x3f, qmp->dp_tx2 + QSERDES_V2_TX_TRANSCEIVER_BIAS_EN); >>>>>> + writel(0x10, qmp->dp_tx2 + QSERDES_V2_TX_HIGHZ_DRVR_EN); >>>>>> + writel(0x0a, qmp->dp_tx2 + QSERDES_V2_TX_TX_POL_INV); >>>>> Are you sure that these don't need to be adjusted based on >>>>> qmp->orientation or selected lanes count? >>>>> >>>>> In fact... I don't see orientation handling for DP at all. Don't we need >>>>> it? >>>> Thanks for the review. >>>> >>>> I agree with your reasoning and compared talos 14nm HPG with hana/kona >>>> 7nm PHY HPG; the 7nm COMBO PHY series has orientation/lane-count dependent >>>> configs, but the 14nm PHY series does not. On QCS615 (talos), the TX_* >>>> registers you pointed to are programmed with constant values regardless >>>> of orientation or lane count. This has been confirmed from both the HPG >>>> and the downstream reference driver. >>> Thanks for the confirmation. >>> >>>> For orientation, from reference the only difference is DP_PHY_MODE, which >>>> is set by qmp_usbc_configure_dp_mode(). The DP PHY does have an >>>> SW_PORTSELECT-related register, but due to talos lane mapping from the >>>> DP controller to the PHY not being the standard <0 1 2 3> sequence, it >>>> cannot reliably handle orientation flip. Also, QCS615 is a fixed- >>>> orientation platform (not DP-over-TypeC), so there is no validated hardware >>>> path for orientation flip on this platform. >>> Wait... I thought that the the non-standard lane order is handled by the >>> DP driver, then we should be able to handle the orientation inside PHY >>> driver as usual. >> >> Yes, I have confirmed this with our verification team. >> >> For the non-standard lane order, handling flip requires swapping mapped  >> lane 0 ↔ lane 3 and lane 1 ↔ lane 2 in the logical2physical mapping. >> This is a hardware limitation, and with the current PHY driver we cannot >> propagate orientation status to dp_ctrl for processing. > This might mean that we might need to make DP host receive mux > messages... Yeah, downstream handles this by passing orientation and lane_cnt info via the DP_PHY_SPARE0 PHY register. But even with that approach, dp_ctrl would still  need access PHY address area. Let's see if there’s any follow-up on extending this in the future. >> >>> Anyway, please add a FIXME comment into the source file and a note to >>> the commit message that SW_PORTSELECT should be handled, but it's not a >>> part of this patch for the stated reasons. >> >> OK, I will add a |FIXME| comment in |qmp_usbc_dp_power_on| and update the >> related commit message. > Thanks! >