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Mon, 12 May 2025 22:42:28 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1747082548; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wWLL8SXxaDrHsmjoDkrhtKmQby8WHNCD8s1a74YU7+8=; b=RFQZ02rBHjUQCIZLYQEaMZn38oPSVM1/LuHrmeQlJffCxoISGZ/KZihlMGeuvbo5RQgfzj bqZPnC8AjlZxZ99NAk9cDcX1e9ajfPzBCDg/mWT5JEriDylCQmtRDmJuVppLFPCGIFkB4O cO8mOV4eQrWx5l1GMFbPrvZplUS3cykWjoqI+OwnHemmGepBoy6hugM15Oh+krT3woDj3N 1A5o3aQ727yR2ZZpB95qeqeg3IaroRYFkwNXsWpowWYn+1+Lh0pDWGGmS2n87BQocflIKe DcdE3NFmxRiEYwAmDExAH7FPht2ybOWPudu8w5tXaZuIrfMUWYgeWTMVLI6VhA== Message-ID: <84cc6341-a2c1-4e3c-8c9e-2bc6589c52a6@mailbox.org> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1747082545; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wWLL8SXxaDrHsmjoDkrhtKmQby8WHNCD8s1a74YU7+8=; b=jwQwBf28noG1EfxvsMWTvb8VBv6jfgaoj3Z2EzGnVRAZe4uPzWVo1ot8ZAzoxLgPV3QfsO xI1oymiEb6QlZwcZGx295e+uM6GlsVvUyxRlcF11nQGo3ALXUyLS7DlLBYL7BOlpct8BCm z+t6wcUpHy/m8qeOv6PhtZTzLrmR1eYrlQxp+2JRKh4i2XIGM9WOkcnT39qeDbalGSXovL 3ZnMMiic0RrOMxKTPe2NI0TUGQOsQc/W152jwmGseOZX71eAgzEQme6/QpU9RiuWWg03h1 wN97+CQGpg2ri3oWCIG+oiLjSrNRSBZV3mJtdrJ9y1bEljAUhX/v8UmKcNk79A== Date: Mon, 12 May 2025 22:42:20 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH v2 1/4] dt-bindings: PCI: rcar-gen4-pci-host: Document optional aux clock To: Manivannan Sadhasivam , Marek Vasut Cc: linux-arm-kernel@lists.infradead.org, =?UTF-8?Q?Niklas_S=C3=B6derlund?= , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= , Aradhya Bhatia , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Heiko Stuebner , Junhao Xie , Kever Yang , Krzysztof Kozlowski , Kuninori Morimoto , Lorenzo Pieralisi , Magnus Damm , Neil Armstrong , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org References: <20250406144822.21784-1-marek.vasut+renesas@mailbox.org> <20250406144822.21784-2-marek.vasut+renesas@mailbox.org> <2ny7jhcp2g5ixo75donutncxnjdawzev3mw7cytvhbk6szl3ue@vixax5lwpycw> Content-Language: en-US From: Marek Vasut In-Reply-To: <2ny7jhcp2g5ixo75donutncxnjdawzev3mw7cytvhbk6szl3ue@vixax5lwpycw> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-MBO-RS-ID: 39ed119621876b7bcad X-MBO-RS-META: 18mqeswom1weurmm9iatqr45af155u75 On 5/9/25 9:37 PM, Manivannan Sadhasivam wrote: > On Sun, Apr 06, 2025 at 04:45:21PM +0200, Marek Vasut wrote: >> Document 'aux' clock which are used to supply the PCIe bus. This >> is useful in case of a hardware setup, where the PCIe controller >> input clock and the PCIe bus clock are supplied from the same >> clock synthesiser, but from different differential clock outputs: > > How different is this clock from the 'reference clock'? I'm not sure what you > mean by 'PCIe bus clock' here. AFAIK, endpoint only takes the reference clock > and the binding already has 'ref' clock for that purpose. So I don't understand > how this new clock is connected to the endpoint device. See the ASCII art below , CLK_DIF0 is 'ref' clock that feeds the controller side, CLK_DIF1 is the bus (or 'aux') clock which feeds the bus (or endpoint) side. Both clock come from the same clock synthesizer, but from two separate clock outputs of the synthesizer. >> ____________ _____________ >> | R-Car PCIe | | PCIe device | >> | | | | >> | PCIe RX<|==================|>PCIe TX | >> | PCIe TX<|==================|>PCIe RX | >> | | | | >> | PCIe CLK<|======.. ..======|>PCIe CLK | >> '------------' || || '-------------' >> || || >> ____________ || || >> | 9FGV0441 | || || >> | | || || >> | CLK DIF0<|======'' || >> | CLK DIF1<|=========='' >> | CLK DIF2<| >> | CLK DIF3<| >> '------------'