From: Ben Dooks <ben.dooks@codethink.co.uk>
To: Conor Dooley <conor.dooley@microchip.com>,
Eric Lin <eric.lin@sifive.com>
Cc: conor@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com,
paul.walmsley@sifive.com, aou@eecs.berkeley.edu, maz@kernel.org,
chenhuacai@kernel.org, baolu.lu@linux.intel.com, will@kernel.org,
kan.liang@linux.intel.com, nnac123@linux.ibm.com,
pierre.gondois@arm.com, huangguangbin2@huawei.com,
jgross@suse.com, chao.gao@intel.com, maobibo@loongson.cn,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, dslin1010@gmail.com,
Zong Li <zong.li@sifive.com>, Nick Hu <nick.hu@sifive.com>
Subject: Re: [PATCH 3/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
Date: Fri, 16 Jun 2023 11:37:42 +0100 [thread overview]
Message-ID: <8525e073-90cd-dde7-5d4b-e4309cd3a657@codethink.co.uk> (raw)
In-Reply-To: <20230616-renovate-country-12b9873b4494@wendy>
On 16/06/2023 11:10, Conor Dooley wrote:
> Hey Eric,
>
> On Fri, Jun 16, 2023 at 02:32:10PM +0800, Eric Lin wrote:
>> This add YAML DT binding documentation for SiFive Private L2
>> cache controller
>>
>> Signed-off-by: Eric Lin <eric.lin@sifive.com>
>> Reviewed-by: Zong Li <zong.li@sifive.com>
>> Reviewed-by: Nick Hu <nick.hu@sifive.com>
>
> Firstly, bindings need to come before the driver using them.
>
>> ---
>> .../bindings/riscv/sifive,pL2Cache0.yaml | 81 +++++++++++++++++++
>> 1 file changed, 81 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/riscv/sifive,pL2Cache0.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/riscv/sifive,pL2Cache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,pL2Cache0.yaml
>> new file mode 100644
>> index 000000000000..b5d8d4a39dde
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/riscv/sifive,pL2Cache0.yaml
>
> Cache bindings have moved to devicetree/bindings/cache.
>
>> @@ -0,0 +1,81 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +# Copyright (C) 2023 SiFive, Inc.
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/riscv/sifive,pL2Cache0.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: SiFive Private L2 Cache Controller
>> +
>> +maintainers:
>> + - Greentime Hu <greentime.hu@sifive.com>
>> + - Eric Lin <eric.lin@sifive.com>
>
> Drop the alignment here please.
>
>> +
>> +description:
>> + The SiFive Private L2 Cache Controller is per hart and communicates with both the upstream
>> + L1 caches and downstream L3 cache or memory, enabling a high-performance cache subsystem.
>> + All the properties in ePAPR/DeviceTree specification applies for this platform.
>
> Please wrap before 80 characters.
>
>> +
>> +allOf:
>> + - $ref: /schemas/cache-controller.yaml#
>> +
>> +select:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - sifive,pL2Cache0
>> + - sifive,pL2Cache1
>
> Why is this select: required?
>
>> + required:
>> + - compatible
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - enum:
>> + - sifive,pL2Cache0
>> + - sifive,pL2Cache1
>
> What is the difference between these? (and drop the caps please)
>
> Should this also not fall back to "cache"?
I thought cache is required as the last resort.
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
next prev parent reply other threads:[~2023-06-16 11:07 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-16 6:32 [PATCH 0/3] Add SiFive Private L2 cache and PMU driver Eric Lin
2023-06-16 6:32 ` [PATCH 1/3] soc: sifive: Add SiFive private L2 cache support Eric Lin
2023-06-16 8:30 ` Ben Dooks
2023-06-23 8:21 ` Eric Lin
2023-06-16 19:02 ` Christophe JAILLET
2023-06-23 8:28 ` Eric Lin
2023-06-16 21:05 ` Conor Dooley
2023-06-23 9:49 ` Eric Lin
2023-06-16 6:32 ` [PATCH 2/3] soc: sifive: Add SiFive private L2 cache PMU driver Eric Lin
2023-06-16 10:12 ` Conor Dooley
2023-06-20 3:14 ` Eric Lin
2023-06-21 15:17 ` Conor Dooley
2023-06-23 13:24 ` Will Deacon
2023-06-23 16:03 ` Eric Lin
2023-07-11 8:41 ` Ben Dooks
2023-06-16 19:05 ` Christophe JAILLET
2023-06-16 6:32 ` [PATCH 3/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller Eric Lin
2023-06-16 10:10 ` Conor Dooley
2023-06-16 10:37 ` Ben Dooks [this message]
2023-06-26 3:06 ` Eric Lin
2023-06-16 10:45 ` Krzysztof Kozlowski
2023-06-26 3:26 ` Eric Lin
2023-06-26 6:19 ` Krzysztof Kozlowski
2023-06-28 16:31 ` Eric Lin
2023-07-01 8:22 ` Krzysztof Kozlowski
2023-07-12 11:09 ` Eric Lin
2023-07-12 12:30 ` Krzysztof Kozlowski
2023-07-12 12:48 ` Conor Dooley
2023-07-20 10:16 ` Eric Lin
2023-07-20 9:49 ` Eric Lin
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