From: Stephen Boyd <sboyd@kernel.org>
To: Conor Dooley <conor@kernel.org>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh@kernel.org>,
Xingyu Wu <xingyu.wu@starfivetech.com>
Cc: Emil Renner Berthing <kernel@esmil.dk>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Hal Feng <hal.feng@starfivetech.com>,
Xingyu Wu <xingyu.wu@starfivetech.com>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v4 1/2] clk: starfive: jh7110-sys: Add notifier for PLL clock
Date: Wed, 10 Apr 2024 00:58:12 -0700 [thread overview]
Message-ID: <858299c27c63aa2974b169f9adf624e9.sboyd@kernel.org> (raw)
In-Reply-To: <20240410033148.213991-2-xingyu.wu@starfivetech.com>
Quoting Xingyu Wu (2024-04-09 20:31:47)
> diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> index 8f5e5abfa178..adf62e4d94e4 100644
> --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> @@ -385,6 +385,32 @@ int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
> }
> EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);
>
> +/*
> + * This clock notifier is called when the rate of PLL0 clock is to be change,
s/change,/changed./
> + * The cpu_root clock should save curent parent clock and swicth its parent
s/swicth/switch/
> + * clock to osc before PLL0 rate will be changed. And switch its parent clock
> + * back after PLL rate finished.
next prev parent reply other threads:[~2024-04-10 7:58 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-10 3:31 [PATCH v4 0/2] Add notifier for PLL0 clock and set it 1.5GHz on Xingyu Wu
2024-04-10 3:31 ` [PATCH v4 1/2] clk: starfive: jh7110-sys: Add notifier for PLL clock Xingyu Wu
2024-04-10 7:58 ` Stephen Boyd [this message]
2024-04-12 8:48 ` Xingyu Wu
2024-04-10 3:31 ` [PATCH v4 2/2] riscv: dts: starfive: visionfive-2: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz Xingyu Wu
2024-04-24 20:32 ` [PATCH v4 0/2] Add notifier for PLL0 clock and set it 1.5GHz on Alexandre Ghiti
2024-04-25 9:08 ` Xingyu Wu
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