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Sat, 03 May 2025 19:59:24 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 543JxN26011254 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 3 May 2025 19:59:23 GMT Received: from [10.110.124.144] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sat, 3 May 2025 12:59:22 -0700 Message-ID: <858be1b7-0183-47b3-97b5-7d162b5748d3@quicinc.com> Date: Sat, 3 May 2025 12:59:21 -0700 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC/WIP 1/4] arm64: dts: qcom: sm8750: Add display (MDSS) with Display CC To: Dmitry Baryshkov CC: Konrad Dybcio , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jessica Zhang , Abhinav Kumar , Abel Vesa , , , References: <20250424-sm8750-display-dts-v1-0-6fb22ca95f38@linaro.org> <20250424-sm8750-display-dts-v1-1-6fb22ca95f38@linaro.org> <81205948-ae43-44ee-aa07-e490ea3bba23@oss.qualcomm.com> <97ae84c6-0807-4b19-a474-ba76cc049da9@quicinc.com> Content-Language: en-US From: Abhinav Kumar In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: EU6cvjXVlfm9R-JQxbk96ugi01DbXM0w X-Proofpoint-ORIG-GUID: EU6cvjXVlfm9R-JQxbk96ugi01DbXM0w X-Authority-Analysis: v=2.4 cv=baZrUPPB c=1 sm=1 tr=0 ts=6816759c cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=KKAkSRfTAAAA:8 a=eIBSfAiRY9SfulBmUi8A:9 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAzMDE4NSBTYWx0ZWRfX/9Go+m0Qt8aB YKLhSZf6U9cZW2e+mngmivFMeBpfPzUpyX3eCfnviFZayr3tqp2PdjtuCQSZNAHKdSdPSuA7zrq fik1odFVWXdpIabVakYZPhswmT6a7A2HuQKO50l/5d18sZRwCrp3kNDh7LNdKNGXfdtTogKjN6s So9dm6mxhWAA5lUhuU15lJMVSqNJ4nHPoldlKlRuQqIb2VWqpOHkO9SDP8tNUde9ika714AKKYd 73W4nONCzcILLnHcCAx8DnuhMgcrxuISwiCu7OW6j3AByx32tITH+LK7f2by5MOERBg3j8Y/2Az iUWq6GJC1OdMtZdmeyXRPkYXyKZJ+A4FTFcmDCOxfzqhU7YVEk/hROcmGC+q54oQNXhH7b/D7aj KqkYe90cZVT6Sg23mjDwflXZ82eWFovEC1PZ2qx8zfdCtCdAMkFj5jPqxZ+PNCE8wbGhYPbL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-03_08,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 impostorscore=0 bulkscore=0 phishscore=0 mlxlogscore=977 clxscore=1015 suspectscore=0 spamscore=0 adultscore=0 mlxscore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505030185 On 5/2/2025 10:51 PM, Dmitry Baryshkov wrote: > On Tue, Apr 29, 2025 at 04:07:24PM -0700, Abhinav Kumar wrote: >> >> >> On 4/28/2025 2:31 PM, Konrad Dybcio wrote: >>> On 4/24/25 3:04 PM, Krzysztof Kozlowski wrote: >>>> Add device nodes for entire display: MDSS, DPU, DSI, DSI PHYs, >>>> DisplayPort and Display Clock Controller. >>>> >>>> Signed-off-by: Krzysztof Kozlowski >>>> >>>> --- >>> >>> [...] >>> >>>> + mdp_opp_table: opp-table { >>>> + compatible = "operating-points-v2"; >>>> + >>> >>> The computer tells me there's also a 156 MHz rate @ SVS_D1 >>> >>> Maybe Abhinav could chime in whether we should add it or not >>> >> >> Yes I also see a 156Mhz for LOW_SVS_D1 but we had a similar entry even for >> sm8650 and did not publish it in the dt. >> >> It was present till sm8450.dtsi but dropped in sm8550/sm8650 even though >> LOW_SVS_D1 is present even on those. >> >> I think the reason could be that the displays being used on the reference >> boards will need a pixel clock of atleast >= low_svs and the MDP clock >> usually depends on the value of the DSI pixel clock (which has a fixed >> relationship to the byte clock) to maintain the data rate. So as a result >> perhaps even if we add it, for most displays this level will be unused. >> >> If we end up using displays which are so small that the pixel clock >> requirement will be even lower than low_svs, we can add those. >> >> OR as an alternative, we can leave this patch as it is and add the >> low_svs_d1 for all chipsets which support it together in another series that >> way it will have the full context of why we are adding it otherwise it will >> look odd again of why sm8550/sm8650 was left out but added in sm8750. > > I think it's better to describe hardware accurately, even if the > particular entry ends up being unused. I'd vote for this option. > >>> [...] >>> >>>> + mdss_dsi_opp_table: opp-table { >>>> + compatible = "operating-points-v2"; >>>> + >>> >>> Similarly there's a 140.63 MHz rate at SVS_D1, but it seems odd >>> with the decimals >> >> For this one, yes its true that LOW_SVS_D1 is 140.63Mhz for sm8750 but this >> voltage corner was somehow never used for DSI byte clock again I am thinking >> this is because for the display resolutions we use, we will always be >= >> low_svs so the low_svs_d1 will never hit even if we add it. > > Please add all voltage/frequency corners. Think about low-res DP or > low-res, low-rate WB. > Sounds good, lets go ahead and add all the voltage/freq corners. Like I noted, even for sm8550/sm8650 the low_svs_d1 was missed out, so if we are adding it for sm8750 now in this series, a follow up patch should also be sent to add them for sm8550/sm8650 as well. That way we will fix them all up together and this does not come across as a discrepancy.