[PATCH v2 0/4] Add support for APPS SMMU on QCS615

[PATCH v2 0/4] Add support for APPS SMMU on QCS615

[Qingqing Zhou]

Enable APPS SMMU function on QCS615 platform. APPS SMMU is required
for address translation in devices including Ethernet/UFS/USB and
so on.

Add the SCM node for SMMU probing normally. SMMU driver probe will
check qcom_scm ready or not, without SCM node, SMMU driver probe will
defer.
The dmesg log without SCM node:
platform 15000000.iommu: deferred probe pending: arm-smmu: qcom_scm not ready

With the SCM node, SMMU can probe normally, but SCM driver still fails
to probe because of one SCM bug:
qcom_scm firmware:scm: error (____ptrval____): Failed to enable the TrustZone memory allocator
qcom_scm firmware:scm: probe with driver qcom_scm failed with error 4
The above SCM bug is fixed by:
https://lore.kernel.org/all/20241005140150.4109700-2-quic_kuldsing@quicinc.com/
But above patch doesn't impact building of current patch series, this patch
series can build successfully without above patch.

Dependency:
https://lore.kernel.org/all/20240926-add_initial_support_for_qcs615-v3-0-e37617e91c62@quicinc.com/

Changes in v2:
- Address the comments on bindings from Krzysztof.
- Improve the commit messages and cover letter.
- Link to v1: https://lore.kernel.org/all/20241011063112.19087-1-quic_qqzhou@quicinc.com/

Qingqing Zhou (4):
  dt-bindings: firmware: qcom,scm: document QCS615 SCM
  dt-bindings: arm-smmu: document QCS615 APPS SMMU
  arm64: dts: qcom: qcs615: add the SCM node
  arm64: dts: qcom: qcs615: add the APPS SMMU node

 .../bindings/firmware/qcom,scm.yaml           |  1 +
 .../devicetree/bindings/iommu/arm,smmu.yaml   |  2 +
 arch/arm64/boot/dts/qcom/qcs615.dtsi          | 81 +++++++++++++++++++
 3 files changed, 84 insertions(+)


base-commit: 0cca97bf23640ff68a6e8a74e9b6659fdc27f48c
prerequisite-patch-id: 3a76212d3a3e930d771312ff9349f87aee5c55d5
prerequisite-patch-id: 8a2454d5e07e56a6dd03f762f498051065635d85
prerequisite-patch-id: 46cdc5640598b60d2f5449af444d6d4e479c00b8
prerequisite-patch-id: 050d1dd8cc9397618e570e6de2d81d0c32c10d7a
prerequisite-patch-id: cd9fc0a399ab430e293764d0911a38109664ca91
prerequisite-patch-id: 07f2c7378c7bbd560f26b61785b6814270647f1b
prerequisite-patch-id: f9680e3c90d8f05babbcadd7b7f5174f484a8275
prerequisite-patch-id: 760a2b8f2acff7a9683bfe8f2d353f7caa6e5580
prerequisite-patch-id: 54b4dd987711302b083f714c6f230726c7781042
prerequisite-patch-id: 624720e543d7857e46d3ee49b8cea413772deb4c
prerequisite-patch-id: 04ca722967256efddc402b7bab94136a5174b0b9
prerequisite-patch-id: ab88a42ec69ad90e8509c9c5b7c6bdd595a7f783
prerequisite-patch-id: 918724fafe43acaa4c4b980bfabe36e9c3212cd1
prerequisite-patch-id: 3bae513ca3da06d6f175502924a1fec6f9424def
prerequisite-patch-id: 57afeee80c9aa069ee243f5a5b634702867d20f1
-- 
2.17.1

[PATCH v2 1/4] dt-bindings: firmware: qcom,scm: document QCS615 SCM

[Qingqing Zhou]

Add the compatible for Qualcomm QCS615 SCM.

Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
---
 Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
index 2cc83771d8e7..2a94d02f11a1 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
@@ -42,6 +42,7 @@ properties:
           - qcom,scm-msm8996
           - qcom,scm-msm8998
           - qcom,scm-qcm2290
+          - qcom,scm-qcs615
           - qcom,scm-qdu1000
           - qcom,scm-sa8775p
           - qcom,scm-sc7180
-- 
2.17.1

[PATCH v2 2/4] dt-bindings: arm-smmu: document QCS615 APPS SMMU

[Qingqing Zhou]

Add the compatible for Qualcomm QCS615 APPS SMMU.

Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
---
 Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index 92d350b8e01a..d3093263d888 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -36,6 +36,7 @@ properties:
         items:
           - enum:
               - qcom,qcm2290-smmu-500
+              - qcom,qcs615-smmu-500
               - qcom,qcs8300-smmu-500
               - qcom,qdu1000-smmu-500
               - qcom,sa8255p-smmu-500
@@ -555,6 +556,7 @@ allOf:
               - cavium,smmu-v2
               - marvell,ap806-smmu-500
               - nvidia,smmu-500
+              - qcom,qcs615-smmu-500
               - qcom,qcs8300-smmu-500
               - qcom,qdu1000-smmu-500
               - qcom,sa8255p-smmu-500
-- 
2.17.1

[PATCH v2 3/4] arm64: dts: qcom: qcs615: add the SCM node

[Qingqing Zhou]

Add the SCM node for QCS615 platform. It is an interface to
communicate to the secure firmware.

Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index ac4c4c751da1..027c5125f36b 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -278,6 +278,13 @@
 		reg = <0 0x80000000 0 0>;
 	};
 
+	firmware {
+		scm {
+			compatible = "qcom,scm-qcs615", "qcom,scm";
+			qcom,dload-mode = <&tcsr 0x13000>;
+		};
+	};
+
 	camnoc_virt: interconnect-0 {
 		compatible = "qcom,qcs615-camnoc-virt";
 		#interconnect-cells = <2>;
-- 
2.17.1

[PATCH v2 4/4] arm64: dts: qcom: qcs615: add the APPS SMMU node

[Qingqing Zhou]

Add the APPS SMMU node for QCS615 platform. Add the dma-ranges
to limit DMA address range to 36bit width to align with system
architecture.

Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615.dtsi | 74 ++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index 027c5125f36b..fcba83fca7cf 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -379,6 +379,7 @@
 	soc: soc@0 {
 		compatible = "simple-bus";
 		ranges = <0 0 0 0 0x10 0>;
+		dma-ranges = <0 0 0 0 0x10 0>;
 		#address-cells = <2>;
 		#size-cells = <2>;
 
@@ -524,6 +525,79 @@
 			reg = <0x0 0x0c3f0000 0x0 0x400>;
 		};
 
+		apps_smmu: iommu@15000000 {
+			compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+			reg = <0x0 0x15000000 0x0 0x80000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <1>;
+
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		intc: interrupt-controller@17a00000 {
 			compatible = "arm,gic-v3";
 			reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
-- 
2.17.1

Re: [PATCH v2 0/4] Add support for APPS SMMU on QCS615

[Krzysztof Kozlowski]

On 15/10/2024 10:15, Qingqing Zhou wrote:
> Enable APPS SMMU function on QCS615 platform. APPS SMMU is required
> for address translation in devices including Ethernet/UFS/USB and
> so on.
> 
> Add the SCM node for SMMU probing normally. SMMU driver probe will
> check qcom_scm ready or not, without SCM node, SMMU driver probe will
> defer.
> The dmesg log without SCM node:
> platform 15000000.iommu: deferred probe pending: arm-smmu: qcom_scm not ready
> 
> With the SCM node, SMMU can probe normally, but SCM driver still fails
> to probe because of one SCM bug:
> qcom_scm firmware:scm: error (____ptrval____): Failed to enable the TrustZone memory allocator
> qcom_scm firmware:scm: probe with driver qcom_scm failed with error 4
> The above SCM bug is fixed by:
> https://lore.kernel.org/all/20241005140150.4109700-2-quic_kuldsing@quicinc.com/
> But above patch doesn't impact building of current patch series, this patch
> series can build successfully without above patch.
> 
> Dependency:
> https://lore.kernel.org/all/20240926-add_initial_support_for_qcs615-v3-0-e37617e91c62@quicinc.com/
> 
> Changes in v2:
> - Address the comments on bindings from Krzysztof.

Which comments? Be specific what changed.

Best regards,
Krzysztof

Re: [PATCH v2 1/4] dt-bindings: firmware: qcom,scm: document QCS615 SCM

[Krzysztof Kozlowski]

On 15/10/2024 10:16, Qingqing Zhou wrote:
> Add the compatible for Qualcomm QCS615 SCM.
> 
> Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>

I give up on this.

Please reach internally to get proper guidance how to send patches and
what to do with tags.

I am not going to do the work twice.

Best regards,
Krzysztof

Re: [PATCH v2 1/4] dt-bindings: firmware: qcom,scm: document QCS615 SCM

[Qingqing Zhou]

在 10/15/2024 4:21 PM, Krzysztof Kozlowski 写道:
> On 15/10/2024 10:16, Qingqing Zhou wrote:
>> Add the compatible for Qualcomm QCS615 SCM.
>>
>> Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
> 
> I give up on this.
> 
> Please reach internally to get proper guidance how to send patches and
> what to do with tags.
Oh, sorry for missing your ack tag, will add in next version. And thanks for your review.
> 
> I am not going to do the work twice.
> 
> Best regards,
> Krzysztof
> 

Re: [PATCH v2 0/4] Add support for APPS SMMU on QCS615

[Qingqing Zhou]

在 10/15/2024 4:20 PM, Krzysztof Kozlowski 写道:
> On 15/10/2024 10:15, Qingqing Zhou wrote:
>> Enable APPS SMMU function on QCS615 platform. APPS SMMU is required
>> for address translation in devices including Ethernet/UFS/USB and
>> so on.
>>
>> Add the SCM node for SMMU probing normally. SMMU driver probe will
>> check qcom_scm ready or not, without SCM node, SMMU driver probe will
>> defer.
>> The dmesg log without SCM node:
>> platform 15000000.iommu: deferred probe pending: arm-smmu: qcom_scm not ready
>>
>> With the SCM node, SMMU can probe normally, but SCM driver still fails
>> to probe because of one SCM bug:
>> qcom_scm firmware:scm: error (____ptrval____): Failed to enable the TrustZone memory allocator
>> qcom_scm firmware:scm: probe with driver qcom_scm failed with error 4
>> The above SCM bug is fixed by:
>> https://lore.kernel.org/all/20241005140150.4109700-2-quic_kuldsing@quicinc.com/
>> But above patch doesn't impact building of current patch series, this patch
>> series can build successfully without above patch.
>>
>> Dependency:
>> https://lore.kernel.org/all/20240926-add_initial_support_for_qcs615-v3-0-e37617e91c62@quicinc.com/
>>
>> Changes in v2:
>> - Address the comments on bindings from Krzysztof.
> 
> Which comments? Be specific what changed.
Got it, will change into "Add QCS615 into compatibles disallowing clocks in arm,smmu.yaml to address the comments in arm,smmu bindings patch from Krzysztof." in next version. Is it fine?
> 
> Best regards,
> Krzysztof
> 

Re: [PATCH v2 4/4] arm64: dts: qcom: qcs615: add the APPS SMMU node

[Konrad Dybcio]

On 15.10.2024 10:16 AM, Qingqing Zhou wrote:
> Add the APPS SMMU node for QCS615 platform. Add the dma-ranges
> to limit DMA address range to 36bit width to align with system
> architecture.
> 
> Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs615.dtsi | 74 ++++++++++++++++++++++++++++
>  1 file changed, 74 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index 027c5125f36b..fcba83fca7cf 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -379,6 +379,7 @@
>  	soc: soc@0 {
>  		compatible = "simple-bus";
>  		ranges = <0 0 0 0 0x10 0>;
> +		dma-ranges = <0 0 0 0 0x10 0>;
>  		#address-cells = <2>;
>  		#size-cells = <2>;
>  
> @@ -524,6 +525,79 @@
>  			reg = <0x0 0x0c3f0000 0x0 0x400>;
>  		};
>  
> +		apps_smmu: iommu@15000000 {
> +			compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500";
> +			reg = <0x0 0x15000000 0x0 0x80000>;
> +			#iommu-cells = <2>;
> +			#global-interrupts = <1>;
> +
> +			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,

The list seems perfectly sorted, which is suspicious.. if we set
i = n - #global-interrupts, interrupt[i] signifies an error in the i-th
context bank. If the order is wrong, we'll get bogus reports

Also, this is not aligned properly ('<' under '<')

Konrad

Re: [PATCH v2 4/4] arm64: dts: qcom: qcs615: add the APPS SMMU node

[Qingqing Zhou]

在 10/18/2024 4:05 AM, Konrad Dybcio 写道:
> On 15.10.2024 10:16 AM, Qingqing Zhou wrote:
>> Add the APPS SMMU node for QCS615 platform. Add the dma-ranges
>> to limit DMA address range to 36bit width to align with system
>> architecture.
>>
>> Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
>> ---
>>  arch/arm64/boot/dts/qcom/qcs615.dtsi | 74 ++++++++++++++++++++++++++++
>>  1 file changed, 74 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> index 027c5125f36b..fcba83fca7cf 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> @@ -379,6 +379,7 @@
>>  	soc: soc@0 {
>>  		compatible = "simple-bus";
>>  		ranges = <0 0 0 0 0x10 0>;
>> +		dma-ranges = <0 0 0 0 0x10 0>;
>>  		#address-cells = <2>;
>>  		#size-cells = <2>;
>>  
>> @@ -524,6 +525,79 @@
>>  			reg = <0x0 0x0c3f0000 0x0 0x400>;
>>  		};
>>  
>> +		apps_smmu: iommu@15000000 {
>> +			compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500";
>> +			reg = <0x0 0x15000000 0x0 0x80000>;
>> +			#iommu-cells = <2>;
>> +			#global-interrupts = <1>;
>> +
>> +			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
>> +					<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
>> +					<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
> 
> The list seems perfectly sorted, which is suspicious.. if we set
> i = n - #global-interrupts, interrupt[i] signifies an error in the i-th
> context bank. If the order is wrong, we'll get bogus reports
Thanks for the review, the list refers to Qualcomm Interrupts design spec, checking this platform again, the list is right, first line is global interrupt and the others are context interrupts with right order.
> 
> Also, this is not aligned properly ('<' under '<')
Got it, will update and align the spaces in next version.
> 
> Konrad

Re: [PATCH v2 4/4] arm64: dts: qcom: qcs615: add the APPS SMMU node

[Qingqing Zhou]

在 10/18/2024 2:20 PM, Qingqing Zhou 写道:
> 
> 
> 在 10/18/2024 4:05 AM, Konrad Dybcio 写道:
>> On 15.10.2024 10:16 AM, Qingqing Zhou wrote:
>>> Add the APPS SMMU node for QCS615 platform. Add the dma-ranges
>>> to limit DMA address range to 36bit width to align with system
>>> architecture.
>>>
>>> Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
>>> ---
>>>  arch/arm64/boot/dts/qcom/qcs615.dtsi | 74 ++++++++++++++++++++++++++++
>>>  1 file changed, 74 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>> index 027c5125f36b..fcba83fca7cf 100644
>>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>> @@ -379,6 +379,7 @@
>>>  	soc: soc@0 {
>>>  		compatible = "simple-bus";
>>>  		ranges = <0 0 0 0 0x10 0>;
>>> +		dma-ranges = <0 0 0 0 0x10 0>;
>>>  		#address-cells = <2>;
>>>  		#size-cells = <2>;
>>>  
>>> @@ -524,6 +525,79 @@
>>>  			reg = <0x0 0x0c3f0000 0x0 0x400>;
>>>  		};
>>>  
>>> +		apps_smmu: iommu@15000000 {
>>> +			compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500";
>>> +			reg = <0x0 0x15000000 0x0 0x80000>;
>>> +			#iommu-cells = <2>;
>>> +			#global-interrupts = <1>;
>>> +
>>> +			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
>>> +					<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
>>> +					<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
>>
>> The list seems perfectly sorted, which is suspicious.. if we set
>> i = n - #global-interrupts, interrupt[i] signifies an error in the i-th
>> context bank. If the order is wrong, we'll get bogus reports
> Thanks for the review, the list refers to Qualcomm Interrupts design spec, checking this platform again, the list is right, first line is global interrupt and the others are context interrupts with right order.
Hi Konrad,
Hope above comments explain your question. If no more questions from you, I will post the next version. Thanks.
>>
>> Also, this is not aligned properly ('<' under '<')
> Got it, will update and align the spaces in next version.
>>
>> Konrad
> 
> 

Re: [PATCH v2 4/4] arm64: dts: qcom: qcs615: add the APPS SMMU node

[Konrad Dybcio]

On 23.10.2024 7:48 AM, Qingqing Zhou wrote:
> 
> 
> 在 10/18/2024 2:20 PM, Qingqing Zhou 写道:
>>
>>
>> 在 10/18/2024 4:05 AM, Konrad Dybcio 写道:
>>> On 15.10.2024 10:16 AM, Qingqing Zhou wrote:
>>>> Add the APPS SMMU node for QCS615 platform. Add the dma-ranges
>>>> to limit DMA address range to 36bit width to align with system
>>>> architecture.
>>>>
>>>> Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
>>>> ---
>>>>  arch/arm64/boot/dts/qcom/qcs615.dtsi | 74 ++++++++++++++++++++++++++++
>>>>  1 file changed, 74 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>> index 027c5125f36b..fcba83fca7cf 100644
>>>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>> @@ -379,6 +379,7 @@
>>>>  	soc: soc@0 {
>>>>  		compatible = "simple-bus";
>>>>  		ranges = <0 0 0 0 0x10 0>;
>>>> +		dma-ranges = <0 0 0 0 0x10 0>;
>>>>  		#address-cells = <2>;
>>>>  		#size-cells = <2>;
>>>>  
>>>> @@ -524,6 +525,79 @@
>>>>  			reg = <0x0 0x0c3f0000 0x0 0x400>;
>>>>  		};
>>>>  
>>>> +		apps_smmu: iommu@15000000 {
>>>> +			compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500";
>>>> +			reg = <0x0 0x15000000 0x0 0x80000>;
>>>> +			#iommu-cells = <2>;
>>>> +			#global-interrupts = <1>;
>>>> +
>>>> +			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
>>>> +					<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
>>>> +					<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
>>>
>>> The list seems perfectly sorted, which is suspicious.. if we set
>>> i = n - #global-interrupts, interrupt[i] signifies an error in the i-th
>>> context bank. If the order is wrong, we'll get bogus reports
>> Thanks for the review, the list refers to Qualcomm Interrupts design spec, checking this platform again, the list is right, first line is global interrupt and the others are context interrupts with right order.
> Hi Konrad,
> Hope above comments explain your question. If no more questions from you, I will post the next version. Thanks.

Sorry, forgot to reply.

I was able to confirm this is just a happy coincidence with the numbers.

Konrad