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Thu, 20 Feb 2020 06:56:28 +0000 Subject: Re: [PATCH] devicetree: zynqmp.dtsi: Add bootmode selection support To: =?UTF-8?B?VmVzYSBKw6TDpHNrZWzDpGluZW4=?= , robh+dt@kernel.org, michal.simek@xilinx.com, mark.rutland@arm.com, devicetree@vger.kernel.org CC: m.tretter@pengutronix.de, nava.manne@xilinx.com, rajan.vaja@xilinx.com, manish.narani@xilinx.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20200219122036.24575-1-mike.looijmans@topic.nl> <07c68809-f65f-91ff-62eb-f12aa8960634@gmail.com> From: Mike Looijmans Organization: TOPIC Message-ID: <85a5807e-1d66-867f-1d83-36e8a054a511@topic.nl> Date: Thu, 20 Feb 2020 07:56:27 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 In-Reply-To: <07c68809-f65f-91ff-62eb-f12aa8960634@gmail.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-CA Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: AM0PR0102CA0050.eurprd01.prod.exchangelabs.com (2603:10a6:208::27) To DB3PR0402MB3947.eurprd04.prod.outlook.com (2603:10a6:8:7::19) MIME-Version: 1.0 Received: from [192.168.80.121] (81.173.50.109) by AM0PR0102CA0050.eurprd01.prod.exchangelabs.com (2603:10a6:208::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2750.18 via Frontend Transport; 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X-MS-Office365-Filtering-Correlation-Id-Prvs: 75b0d43c-6314-4b94-67c7-08d7b5d20282 X-Forefront-PRVS: 031996B7EF X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BwsniFGXMK7k3k9avVv7k4YDBTeaeIPOLouOH+QGQiTXHF7PNZ94CRVCzs8atK4XPyGKoAiP18nc/XdZAGgXv6OcdbliCi6hmm7Cg/y7P4u1nwGU0jeL7iU4Y20fjhs2wx7TwvDaUoHj8BTgfQfv47btaQxUKJuCOnCRwFwGxHGxhdFY4zdiwd15zoGGpfHDF6UPEVuFznt/R0+0h7Ob2navrj7RRq9gb7o8LnsmMsQeREovKKK1Hb+QPn+0lrtOLRXovLAbejP0xiQGAWSpAGGhdKFnRvOAa4y1OsbEXWRfqu73Pt2k+pDxbcuzC7Jwl/GoJkuiwqdjipI3WmIBXE5Lqf9E273KHpEBwabcnm/lmwIWXLwATWSljQT3foxkJYZoKdjzFhwOl6R2ZF7sVo3xbGwI3jXuYQzas4KO4sXDU/ApqDYllzhKjcpZvJvhnOEevKcvWlWPKLkVfKZ5fHVcuxwXmLlfitVCjye6QQPvEzL9EV/mvycnaMrHy07a X-OriginatorOrg: topic.nl X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Feb 2020 06:56:32.8118 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0e66adc1-56bd-497a-0dfe-08d7b5d20535 X-MS-Exchange-CrossTenant-Id: 449607a5-3517-482d-8d16-41dd868cbda3 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=449607a5-3517-482d-8d16-41dd868cbda3;Ip=[13.81.10.179];Helo=[westeu13-emailsignatures-cloud.codetwo.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB5186 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 19-02-2020 19:23, Vesa J=C3=A4=C3=A4skel=C3=A4inen wrote: > Hi Mike, >=20 > On 19.2.2020 14.20, Mike Looijmans wrote: >> Add bootmode override support for ZynqMP devices. Allows one to select >> a boot device by running "reboot qspi32" for example. Activate config >> item CONFIG_SYSCON_REBOOT_MODE to make this work. >> >> Signed-off-by: Mike Looijmans >> --- >> =C2=A0 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 24 +++++++++++++++++++++= +++ >> =C2=A0 1 file changed, 24 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi=20 >> b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >> index 26d926eb1431..4c38d77ecbba 100644 >> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >> @@ -246,6 +246,30 @@ >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 }; >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 }; >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* Clock and Reset control r= egisters for LPD */ >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 lpd_apb: apb@ff5e0000 { >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 comp= atible =3D "syscon", "simple-mfd"; >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 reg = =3D <0x0 0xff5e0000 0x0 0x400>; >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 rebo= ot-mode { >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 compatible =3D "syscon-reboot-mode"; >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 offset =3D <0x200>; >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 mask =3D <0xf100>; >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 /* Bit(8) is the "force user" bit */ >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 mode-normal =3D <0x0000>; >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 mode-psjtag =3D <0x0100>; >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 mode-qspi24 =3D <0x1100>; >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 mode-qspi32 =3D <0x2100>; >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 mode-sd0=C2=A0=C2=A0=C2=A0 =3D <0x3100>; >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 mode-nand=C2=A0=C2=A0 =3D <0x4100>; >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 mode-sd1=C2=A0=C2=A0=C2=A0 =3D <0x6100>; >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 mode-emmc=C2=A0=C2=A0 =3D <0x6100>; >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 mode-usb0=C2=A0=C2=A0 =3D <0x7100>; >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 mode-pjtag0 =3D <0x8100>; >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 mode-pjtag1 =3D <0x9100>; >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 mode-sd1ls=C2=A0 =3D <0xe100>; >=20 > This kinda looks a bit misuse of reboot mode support. >=20 > Usually you are signal with reboot-mode that you want to do factory reset= ,=20 > enter recovery mode or such things. >=20 > Now this signaling here is telling that this is used for selecting from w= hat=20 > device to boot from. On the ZynqMP this is the only way to communicate with the ROM. > Another problem is that this now modifies all Xilinx Zynq MPSoCs which is= =20 > kinda wrong. This behavior should really be product/board specific and no= t=20 > common for all boards -- undoing this in product/board is somewhat cumber= some.=20 The boot mode setting is in the SOC, and is not board specific. The ROM=20 interprets this field. The only board specific thing is that you may not=20 actually have a NAND chip attached to it. My idea was that a board could easily add say 'mode-recovery=3D<0x2100>;' t= o=20 make the QPSI boot the method of recovery. The bootloader also has access t= o=20 this register, so it can see that there was a boot mode override in effect. > Now this change hijacks the "reboot " with this behavior which is no= t so=20 > nice. If anyone has a better suggestion as to where this should go, I'd be more t= han=20 happy to hear about it. It's the only interface that I could find in the=20 kernel to attach a bootmode override to.