From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3509D21018F; Thu, 8 May 2025 08:42:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746693750; cv=none; b=JxfaRfW/wCKyxqK3ISu6/CRwmPD18q9wg3yv/8ETZeKpIhvJyVnEbLSuGxtzzdkCbU5N8m1aBhwkaht0UJLDj+KxoaT2nNssVfwimBH/n7720SGxNBdkIV6BSMwWhKv6WepKfKlqYYZOZVNzIwRe7M1MV85+SDp+lFaEX8y14IY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746693750; c=relaxed/simple; bh=r4rhd827Fnak6aKEMgLnJgrNTLGWxl8VcUCjQ0+pR6c=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=p2Yh8gRcuS+9NvcFhhluP2mDB27BjEmC3/zAJDVQKrRnCxR8ZuS958GbsARmKm8YKTWJPhBdf6pGqVU0dm4sQ2ZJqalUjTUqse2i8lxcx4V6k+LY8ot3DGoj8mk15JgwqvCFbeVILt5RLHfiKdYkFJKIo8GsxQxbQvgwTraGvcY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=o1ExFhJt; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="o1ExFhJt" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9D702C4CEE7; Thu, 8 May 2025 08:42:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746693749; bh=r4rhd827Fnak6aKEMgLnJgrNTLGWxl8VcUCjQ0+pR6c=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=o1ExFhJtUJGWLWfvwRKP+t5Nhas05Da6Xm1+IvL1UlXP/NqPHx1hDNUGWOZ1cG9Hg ZvAsxplF2LvV2IIDPZIlv2kmxjTpqKhxrml8Ty3viPQ2sB2MhbKb6EqYp/i4cuqxLE 0yu0HdiirY6VYYLM6kBMxtkSLAhIPr3fjGvnumfN3oLjtSxvIwufoxvsV0MAUz+qtA Wwqt7FIYgfQWsR8v3ETkEIGYI1UrgEP9fIu2GpCa0Tkv9cpo0pxhXGsW0Uv3RqWgrx LF3E4chMDfjTE0ojemPPZtvjx/nxsTowQmypdUkTmjmPRUjCfMHIPTH80ixvtWE7/x xF/R63bxc/bAg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uCwpn-00CwFr-F3; Thu, 08 May 2025 09:42:27 +0100 Date: Thu, 08 May 2025 09:42:27 +0100 Message-ID: <864ixvh4ss.wl-maz@kernel.org> From: Marc Zyngier To: Lorenzo Pieralisi Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , Jiri Slaby , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v3 20/25] irqchip/gic-v5: Add GICv5 PPI support In-Reply-To: References: <20250506-gicv5-host-v3-0-6edd5a92fd09@kernel.org> <20250506-gicv5-host-v3-20-6edd5a92fd09@kernel.org> <87zffpn5rk.ffs@tglx> <86a57ohjey.wl-maz@kernel.org> <87ecx0mt9p.ffs@tglx> <867c2sh6jx.wl-maz@kernel.org> <874ixwmpto.ffs@tglx> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: lpieralisi@kernel.org, tglx@linutronix.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, sascha.bischoff@arm.com, timothy.hayes@arm.com, Liam.Howlett@oracle.com, mark.rutland@arm.com, jirislaby@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 08 May 2025 08:42:41 +0100, Lorenzo Pieralisi wrote: > > On Wed, May 07, 2025 at 04:57:07PM +0200, Thomas Gleixner wrote: > > On Wed, May 07 2025 at 14:52, Marc Zyngier wrote: > > > On Wed, 07 May 2025 14:42:42 +0100, > > > Thomas Gleixner wrote: > > >> > > >> On Wed, May 07 2025 at 10:14, Marc Zyngier wrote: > > >> > On Tue, 06 May 2025 16:00:31 +0100, > > >> > Thomas Gleixner wrote: > > >> >> > > >> >> How does this test distinguish between LEVEL_LOW and LEVEL_HIGH? It only > > >> >> tests for level, no? So the test is interesting at best ... > > >> > > > >> > There is no distinction between HIGH and LOW, RISING and FALLING, in > > >> > any revision of the GIC architecture. > > >> > > >> Then pretending that there is a set_type() functionality is pretty daft > > > > > > You still need to distinguish between level and edge when this is > > > programmable (which is the case for a subset of the PPIs). > > > > Fair enough, but can we please add a comment to this function which > > explains this oddity. > > Getting back to this, I would need your/Marc's input on this. > > I think it is fair to remove the irq_set_type() irqchip callback for > GICv5 PPIs because there is nothing to set, as I said handling mode > for these IRQs is fixed. I don't think this can cause any trouble > (IIUC a value within the IRQF_TRIGGER_MASK should be set on requesting > an IRQ to "force" the trigger to be programmed and even then core code > would not fail if the irq_set_type() irqchip callback is not > implemented). > > I am thinking about *existing* drivers that request GICv3 PPIs with > values in IRQF_TRIGGER_MASK set (are there any ? Don't think so but you > know better than I do), when we switch over to GICv5 we would have no > irq_set_type() callback for PPIs but I think we are still fine, not > implementing irqchip.irq_set_type() is correct IMO. Nobody seems to use a hardcoded trigger (well, there is one exception, but that's to paper over a firmware bug). > On the other hand, given that on GICv5 PPI handling mode is fixed, > do you think that in the ppi_irq_domain_ops.translate() callback, > I should check the type the firmware provided and fail the translation > if it does not match the HW hardcoded value ? Why? The fact that the firmware is wrong doesn't change the hardware integration. It just indicates that whoever wrote the firmware didn't read the documentation. Even more, I wonder what the benefit of having that information in the firmware tables if the only thing that matters in the immutable HW view. Yes, having it in the DT/ACPI simplifies the job of the kernel (only one format to parse). But it is overall useless information. > Obviously if firmware exposes the wrong type that's a firmware bug > but I was wondering whether it is better to fail the firmware-to-Linux > IRQ translation if the firmware provided type is wrong rather than carry > on pretending that the type is correct (I was abusing the irq_set_type() > callback to do just that - namely, check that the type provided by > firmware matches HW but I think that's the wrong place to put it). I don't think there is anything to do. Worse case, you spit a pr_warn_once() and carry on. Thanks, M. -- Without deviation from the norm, progress is not possible.