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Subject: Re: [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support
From:   Xi Ruoyao <xry111@linuxfromscratch.org>
To:     Jisheng Zhang <jszhang@kernel.org>
Cc:     Conor Dooley <conor.dooley@microchip.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <maz@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
        linux-riscv@lists.infradead.org
Date:   Thu, 27 Jul 2023 08:14:57 +0800
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On Wed, 2023-07-26 at 23:00 +0800, Jisheng Zhang wrote:
> which dts r u using? see below.
>=20
> >=20
> > Or maybe my toolchain (GCC 13.1.0, Binutils-2.40, with no patches) can
> > miscompile the kernel?

/* snip */

> > Boot HART ID=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 : 0
> > Boot HART Domain=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =
: root
> > Boot HART Priv Version=C2=A0=C2=A0=C2=A0 : v1.11
> > Boot HART Base ISA=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 : rv64imaf=
dcvx
>=20
> what? I don't think the mainline dts provide v and x.=20

I copied the compiled arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dtb
into /boot and loaded it with u-boot "load" command onto 0x46000000, and
passed this address to the booti command.

But maybe I've copied the wrong file or made some other mistake... I'll
recheck.