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Januar 2025, 04:34:18 CET schrieb Peng Fan: > On Wed, Jan 08, 2025 at 11:15:40AM +0100, Alexander Stein wrote: > >Hi Peng, > > > >Am Mittwoch, 8. Januar 2025, 08:00:18 CET schrieb Peng Fan (OSS): > >> From: Peng Fan > >>=20 > >> i.MX9 OCOTP supports a specific peripheral or function being fused > >> which means disabled, so > >> - Introduce ocotp_access_gates to be container of efuse gate info > >> - Iterate all nodes to check accessing permission. If not > >> allowed to be accessed, detach the node > >>=20 > >> Signed-off-by: Peng Fan > >> --- > >> drivers/nvmem/imx-ocotp-ele.c | 172 +++++++++++++++++++++++++++++++++= ++++++++- > >> 1 file changed, 171 insertions(+), 1 deletion(-) > >>=20 > [....] > >> + > >> + return imx_ele_ocotp_access_control(priv); > > > >In [1] you mentioned devlink should solve the probe order. How does this > >play when the driver is compiled in (e.g. ethernet for NFS boot) but > >this OCOTP driver is just a module? >=20 > OCOTP needs to built in for using devlink. Or the users needs to be > built as module. I don't like this kind of assumption. Would it make more sense to make CONFIG_NVMEM_IMX_OCOTP_ELE as bool instead of tristate? > >I'm not well versed with devlink, but is > >> access-controllers =3D <&ocotp IMX93_OCOTP_ENET1_GATE>; > >already enough to create that link? >=20 > Yes, the drivers/of/property.c has this > "DEFINE_SIMPLE_PROP(access_controllers, "access-controllers", "#access-co= ntroller-cells")" >=20 > The fw_devlink driver will create consumer/supplier to make sure proper > order. Okay, thanks for confirming. Best regards, Alexander > Regards, > Peng >=20 > > > >Best regards, > >Alexander > > > >> } > >> =20 > >> +struct access_gate imx93_access_gate[] =3D { > >> + [IMX93_OCOTP_NPU_GATE] =3D { .word =3D 19, .mask =3D BIT(13) }, > >> + [IMX93_OCOTP_A550_GATE] =3D { .word =3D 19, .mask =3D BIT(14) }, > >> + [IMX93_OCOTP_A551_GATE] =3D { .word =3D 19, .mask =3D BIT(15) }, > >> + [IMX93_OCOTP_M33_GATE] =3D { .word =3D 19, .mask =3D BIT(24) }, > >> + [IMX93_OCOTP_CAN1_FD_GATE] =3D { .word =3D 19, .mask =3D BIT(28) }, > >> + [IMX93_OCOTP_CAN2_FD_GATE] =3D { .word =3D 19, .mask =3D BIT(29) }, > >> + [IMX93_OCOTP_CAN1_GATE] =3D { .word =3D 19, .mask =3D BIT(30) }, > >> + [IMX93_OCOTP_CAN2_GATE] =3D { .word =3D 19, .mask =3D BIT(31) }, > >> + [IMX93_OCOTP_USB1_GATE] =3D { .word =3D 20, .mask =3D BIT(3) }, > >> + [IMX93_OCOTP_USB2_GATE] =3D { .word =3D 20, .mask =3D BIT(4) }, > >> + [IMX93_OCOTP_ENET1_GATE] =3D { .word =3D 20, .mask =3D BIT(5) }, > >> + [IMX93_OCOTP_ENET2_GATE] =3D { .word =3D 20, .mask =3D BIT(6) }, > >> + [IMX93_OCOTP_PXP_GATE] =3D { .word =3D 20, .mask =3D BIT(10) }, > >> + [IMX93_OCOTP_MIPI_CSI1_GATE] =3D { .word =3D 20, .mask =3D BIT(17) = }, > >> + [IMX93_OCOTP_MIPI_DSI1_GATE] =3D { .word =3D 20, .mask =3D BIT(19) = }, > >> + [IMX93_OCOTP_LVDS1_GATE] =3D { .word =3D 20, .mask =3D BIT(24) }, > >> + [IMX93_OCOTP_ADC1_GATE] =3D { .word =3D 21, .mask =3D BIT(7) }, > >> +}; > >> + > >> +static const struct ocotp_access_gates imx93_access_gates_info =3D { > >> + .num_words =3D 3, > >> + .words =3D {19, 20, 21}, > >> + .num_gates =3D ARRAY_SIZE(imx93_access_gate), > >> + .gates =3D imx93_access_gate, > >> +}; > >> + > >> static const struct ocotp_devtype_data imx93_ocotp_data =3D { > >> + .access_gates =3D &imx93_access_gates_info, > >> .reg_off =3D 0x8000, > >> .reg_read =3D imx_ocotp_reg_read, > >> .size =3D 2048, > >> @@ -183,7 +307,53 @@ static const struct ocotp_devtype_data imx93_ocot= p_data =3D { > >> }, > >> }; > >> =20 > >> +struct access_gate imx95_access_gate[] =3D { > >> + [IMX95_OCOTP_CANFD1_GATE] =3D { .word =3D 17, .mask =3D BIT(20) }, > >> + [IMX95_OCOTP_CANFD2_GATE] =3D { .word =3D 17, .mask =3D BIT(21) }, > >> + [IMX95_OCOTP_CANFD3_GATE] =3D { .word =3D 17, .mask =3D BIT(22) }, > >> + [IMX95_OCOTP_CANFD4_GATE] =3D { .word =3D 17, .mask =3D BIT(23) }, > >> + [IMX95_OCOTP_CANFD5_GATE] =3D { .word =3D 17, .mask =3D BIT(24) }, > >> + [IMX95_OCOTP_CAN1_GATE] =3D { .word =3D 17, .mask =3D BIT(25) }, > >> + [IMX95_OCOTP_CAN2_GATE] =3D { .word =3D 17, .mask =3D BIT(26) }, > >> + [IMX95_OCOTP_CAN3_GATE] =3D { .word =3D 17, .mask =3D BIT(27) }, > >> + [IMX95_OCOTP_CAN4_GATE] =3D { .word =3D 17, .mask =3D BIT(28) }, > >> + [IMX95_OCOTP_CAN5_GATE] =3D { .word =3D 17, .mask =3D BIT(29) }, > >> + [IMX95_OCOTP_NPU_GATE] =3D { .word =3D 18, .mask =3D BIT(0) }, > >> + [IMX95_OCOTP_A550_GATE] =3D { .word =3D 18, .mask =3D BIT(1) }, > >> + [IMX95_OCOTP_A551_GATE] =3D { .word =3D 18, .mask =3D BIT(2) }, > >> + [IMX95_OCOTP_A552_GATE] =3D { .word =3D 18, .mask =3D BIT(3) }, > >> + [IMX95_OCOTP_A553_GATE] =3D { .word =3D 18, .mask =3D BIT(4) }, > >> + [IMX95_OCOTP_A554_GATE] =3D { .word =3D 18, .mask =3D BIT(5) }, > >> + [IMX95_OCOTP_A555_GATE] =3D { .word =3D 18, .mask =3D BIT(6) }, > >> + [IMX95_OCOTP_M7_GATE] =3D { .word =3D 18, .mask =3D BIT(9) }, > >> + [IMX95_OCOTP_DCSS_GATE] =3D { .word =3D 18, .mask =3D BIT(22) }, > >> + [IMX95_OCOTP_LVDS1_GATE] =3D { .word =3D 18, .mask =3D BIT(27) }, > >> + [IMX95_OCOTP_ISP_GATE] =3D { .word =3D 18, .mask =3D BIT(29) }, > >> + [IMX95_OCOTP_USB1_GATE] =3D { .word =3D 19, .mask =3D BIT(2) }, > >> + [IMX95_OCOTP_USB2_GATE] =3D { .word =3D 19, .mask =3D BIT(3) }, > >> + [IMX95_OCOTP_NETC_GATE] =3D { .word =3D 19, .mask =3D BIT(4) }, > >> + [IMX95_OCOTP_PCIE1_GATE] =3D { .word =3D 19, .mask =3D BIT(6) }, > >> + [IMX95_OCOTP_PCIE2_GATE] =3D { .word =3D 19, .mask =3D BIT(7) }, > >> + [IMX95_OCOTP_ADC1_GATE] =3D { .word =3D 19, .mask =3D BIT(8) }, > >> + [IMX95_OCOTP_EARC_RX_GATE] =3D { .word =3D 19, .mask =3D BIT(11) }, > >> + [IMX95_OCOTP_GPU3D_GATE] =3D { .word =3D 19, .mask =3D BIT(16) }, > >> + [IMX95_OCOTP_VPU_GATE] =3D { .word =3D 19, .mask =3D BIT(17) }, > >> + [IMX95_OCOTP_JPEG_ENC_GATE] =3D { .word =3D 19, .mask =3D BIT(18) }, > >> + [IMX95_OCOTP_JPEG_DEC_GATE] =3D { .word =3D 19, .mask =3D BIT(19) }, > >> + [IMX95_OCOTP_MIPI_CSI1_GATE] =3D { .word =3D 19, .mask =3D BIT(21) = }, > >> + [IMX95_OCOTP_MIPI_CSI2_GATE] =3D { .word =3D 19, .mask =3D BIT(22) = }, > >> + [IMX95_OCOTP_MIPI_DSI1_GATE] =3D { .word =3D 19, .mask =3D BIT(23) = }, > >> +}; > >> + > >> +static const struct ocotp_access_gates imx95_access_gates_info =3D { > >> + .num_words =3D 3, > >> + .words =3D {17, 18, 19}, > >> + .num_gates =3D ARRAY_SIZE(imx95_access_gate), > >> + .gates =3D imx95_access_gate, > >> +}; > >> + > >> static const struct ocotp_devtype_data imx95_ocotp_data =3D { > >> + .access_gates =3D &imx95_access_gates_info, > >> .reg_off =3D 0x8000, > >> .reg_read =3D imx_ocotp_reg_read, > >> .size =3D 2048, > >>=20 > >>=20 > > > > >=20 >=20 =2D-=20 TQ-Systems GmbH | M=FChlstra=DFe 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht M=FCnchen, HRB 105018 Gesch=E4ftsf=FChrer: Detlef Schneider, R=FCdiger Stahl, Stefan Schneider http://www.tq-group.com/