From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73EC0C54EBE for ; Fri, 13 Jan 2023 09:49:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231342AbjAMJtK (ORCPT ); Fri, 13 Jan 2023 04:49:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240922AbjAMJr5 (ORCPT ); Fri, 13 Jan 2023 04:47:57 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B968143E42; Fri, 13 Jan 2023 01:39:23 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 348A460B1B; Fri, 13 Jan 2023 09:39:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 88583C433D2; Fri, 13 Jan 2023 09:39:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673602762; bh=VfAdCPcysVT/3jW83ODpVi1gcLL1NcM8uhMQlELECPE=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=CwHnAZ/hDQ3CyGL5y9IFOTkJ0YRLPA7CyI3xuAS6yP2KQ+YXy5xW95h/cPvm5nVJP Kcn7l8Ev0CmXTgPaHPaxErwv2V49MIeTaMpPU05imaC4gGKt89C+OgK9lsclxrN6iq KBg5KddP1c479Svp6CFSQHZfnuSeF03zJbl6Q9QbFJhwvZbQkDpXZzC5R1ROvflZ5/ 8Ko85a8OsG6FYorPRH6uWqa38GQdznlnWTRJgbY45XC5ZIR3mVfOZLMVfsZsfj3HxO hNXPmSwQ7ADu47qtCmImEffoCSmE9ZhQHs4gv9lZJfvbp0kynYJLI0Du+Ize8iinaJ H6KZOlUIMEb5g== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1pGGWs-001SiU-9t; Fri, 13 Jan 2023 09:39:18 +0000 Date: Fri, 13 Jan 2023 09:39:17 +0000 Message-ID: <868ri6ojsq.wl-maz@kernel.org> From: Marc Zyngier To: Anup Patel Cc: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 3/9] irqchip/riscv-intc: Add support for RISC-V AIA In-Reply-To: <20230103141409.772298-4-apatel@ventanamicro.com> References: <20230103141409.772298-1-apatel@ventanamicro.com> <20230103141409.772298-4-apatel@ventanamicro.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: apatel@ventanamicro.com, palmer@dabbelt.com, paul.walmsley@sifive.com, tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, atishp@atishpatra.org, Alistair.Francis@wdc.com, anup@brainfault.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, 03 Jan 2023 14:14:03 +0000, Anup Patel wrote: > > The RISC-V advanced interrupt architecture (AIA) extends the per-HART > local interrupts in following ways: > 1. Minimum 64 local interrupts for both RV32 and RV64 > 2. Ability to process multiple pending local interrupts in same > interrupt handler > 3. Priority configuration for each local interrupts > 4. Special CSRs to configure/access the per-HART MSI controller > > This patch adds support for RISC-V AIA in the RISC-V intc driver. > > Signed-off-by: Anup Patel > --- > drivers/irqchip/irq-riscv-intc.c | 37 ++++++++++++++++++++++++++------ > 1 file changed, 31 insertions(+), 6 deletions(-) > > diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c > index f229e3e66387..880d1639aadc 100644 > --- a/drivers/irqchip/irq-riscv-intc.c > +++ b/drivers/irqchip/irq-riscv-intc.c > @@ -16,6 +16,7 @@ > #include > #include > #include > +#include > > static struct irq_domain *intc_domain; > > @@ -29,6 +30,15 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs) > generic_handle_domain_irq(intc_domain, cause); > } > > +static asmlinkage void riscv_intc_aia_irq(struct pt_regs *regs) What does "static asmlinkage" in a C file even mean? And clearly, this isn't the only instance in this file... > +{ > + unsigned long topi; > + > + while ((topi = csr_read(CSR_TOPI))) > + generic_handle_domain_irq(intc_domain, > + topi >> TOPI_IID_SHIFT); > +} > + > /* > * On RISC-V systems local interrupts are masked or unmasked by writing > * the SIE (Supervisor Interrupt Enable) CSR. As CSRs can only be written > @@ -38,12 +48,18 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs) > > static void riscv_intc_irq_mask(struct irq_data *d) > { > - csr_clear(CSR_IE, BIT(d->hwirq)); > + if (d->hwirq < BITS_PER_LONG) And what if BIT_PER_LONG is 32, as I expect it to be on 32bit, which the commit message says is supported? > + csr_clear(CSR_IE, BIT(d->hwirq)); > + else > + csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); > } > > static void riscv_intc_irq_unmask(struct irq_data *d) > { > - csr_set(CSR_IE, BIT(d->hwirq)); > + if (d->hwirq < BITS_PER_LONG) > + csr_set(CSR_IE, BIT(d->hwirq)); > + else > + csr_set(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); > } > > static void riscv_intc_irq_eoi(struct irq_data *d) > @@ -115,7 +131,7 @@ static struct fwnode_handle *riscv_intc_hwnode(void) > static int __init riscv_intc_init(struct device_node *node, > struct device_node *parent) > { > - int rc; > + int rc, nr_irqs; > unsigned long hartid; > > rc = riscv_of_parent_hartid(node, &hartid); > @@ -133,14 +149,21 @@ static int __init riscv_intc_init(struct device_node *node, > if (riscv_hartid_to_cpuid(hartid) != smp_processor_id()) > return 0; > > - intc_domain = irq_domain_add_linear(node, BITS_PER_LONG, > + nr_irqs = BITS_PER_LONG; > + if (riscv_isa_extension_available(NULL, SxAIA) && BITS_PER_LONG == 32) > + nr_irqs = nr_irqs * 2; Really, please drop this BITS_PER_LONG stuff. Use explicit numbers. M. -- Without deviation from the norm, progress is not possible.