From: Marc Zyngier <marc.zyngier@arm.com>
To: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Mark Rutland <mark.rutland@arm.com>, Andrew Lunn <andrew@lunn.ch>,
Jason Cooper <jason@lakedaemon.net>,
devicetree@vger.kernel.org,
Antoine Tenart <antoine.tenart@bootlin.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Gregory Clement <gregory.clement@bootlin.com>,
Haim Boot <hayim@marvell.com>, Will Deacon <will.deacon@arm.com>,
Maxime Chevallier <maxime.chevallier@bootlin.com>,
Nadav Haklai <nadavh@marvell.com>,
Rob Herring <robh+dt@kernel.org>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Thomas Gleixner <tglx@linutronix.de>,
Hanna Hawa <hannah@marvell.com>,
linux-arm-kernel@lists.infradead.org,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Subject: Re: [PATCH v6 00/14] Add System Error Interrupt support to Armada SoCs
Date: Tue, 02 Oct 2018 11:57:48 +0100 [thread overview]
Message-ID: <86a7nwvcnn.wl-marc.zyngier@arm.com> (raw)
In-Reply-To: <20181001141358.31508-1-miquel.raynal@bootlin.com>
On Mon, 01 Oct 2018 15:13:44 +0100,
Miquel Raynal <miquel.raynal@bootlin.com> wrote:
>
> The ICU is an IRQ chip found in Armada CP110. It currently has 207 wired
> inputs. Its purpose is to aggregate all CP interrupts and report them to
> the AP through MSIs. The ICU writes into GIC registers (AP side) by way
> of the interconnect. These interrupts can be of several groups:
> - SecuRe (SR);
> - Non-SecuRe (NSR);
> - System Error Interrupts (SEI);
> - RAM Error Interrupts (REI);
> - ...
> Each ICU wired interrupt can be of any of these groups. The group is
> encoded in the MSI payload.
[...]
I'm now ready to queue patches 1 through to 11 (with patches 6 and 9
as of v7). Who is picking up the DT patches (12 to 14)?
Thanks,
M.
--
Jazz is not dead, it just smell funny.
next prev parent reply other threads:[~2018-10-02 10:57 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-01 14:13 [PATCH v6 00/14] Add System Error Interrupt support to Armada SoCs Miquel Raynal
2018-10-01 14:13 ` [PATCH v6 01/14] genirq/msi: Allow creation of a tree-based irqdomain for platform-msi Miquel Raynal
2018-10-01 14:13 ` [PATCH v6 02/14] dt-bindings/interrupt-controller: fix Marvell ICU length in the example Miquel Raynal
2018-10-01 14:13 ` [PATCH v6 03/14] irqchip/irq-mvebu-icu: fix wrong private data retrieval Miquel Raynal
2018-10-01 14:13 ` [PATCH v6 04/14] irqchip/irq-mvebu-icu: clarify the reset operation of configured interrupts Miquel Raynal
2018-10-01 14:13 ` [PATCH v6 05/14] irqchip/irq-mvebu-icu: disociate ICU and NSR Miquel Raynal
2018-10-01 14:13 ` [PATCH v6 06/14] irqchip/irq-mvebu-icu: support ICU subnodes Miquel Raynal
2018-10-01 16:49 ` Marc Zyngier
2018-10-02 8:13 ` Miquel Raynal
2018-10-02 8:54 ` [PATCH v7 " Miquel Raynal
2018-10-01 14:13 ` [PATCH v6 07/14] irqchip/irq-mvebu-sei: add new driver for Marvell SEI Miquel Raynal
2018-10-01 14:13 ` [PATCH v6 08/14] arm64: marvell: enable SEI driver Miquel Raynal
2018-10-01 14:13 ` [PATCH v6 09/14] irqchip/irq-mvebu-icu: add support for System Error Interrupts (SEI) Miquel Raynal
2018-10-01 17:07 ` Marc Zyngier
2018-10-02 8:18 ` Miquel Raynal
2018-10-02 8:59 ` [PATCH v7 " Miquel Raynal
2018-10-01 14:13 ` [PATCH v6 10/14] dt-bindings/interrupt-controller: update Marvell ICU bindings Miquel Raynal
2018-10-01 14:13 ` [PATCH v6 11/14] dt-bindings/interrupt-controller: add documentation for Marvell SEI controller Miquel Raynal
2018-10-01 14:13 ` [PATCH v6 12/14] arm64: dts: marvell: add AP806 SEI subnode Miquel Raynal
2018-10-02 14:39 ` Gregory CLEMENT
2018-10-01 14:13 ` [PATCH v6 13/14] arm64: dts: marvell: use new bindings for CP110 interrupts Miquel Raynal
2018-10-02 14:41 ` Gregory CLEMENT
2018-10-01 14:13 ` [PATCH v6 14/14] arm64: dts: marvell: add CP110 ICU SEI subnode Miquel Raynal
2018-10-02 10:57 ` Marc Zyngier [this message]
2018-10-02 14:30 ` [PATCH v6 00/14] Add System Error Interrupt support to Armada SoCs Gregory CLEMENT
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