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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Cc: Andy Gross <agross@kernel.org>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konrad.dybcio@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
	Alex Elder <elder@linaro.org>,
	Srini Kandagatla <srinivas.kandagatla@linaro.org>,
	kernel@quicinc.com, linux-arm-msm@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 06/11] firmware: qcom-shm-bridge: new driver
Date: Tue, 29 Aug 2023 18:47:40 +0200	[thread overview]
Message-ID: <86bb50fd-72f3-7c76-c4fe-f8e4765e33d5@linaro.org> (raw)
In-Reply-To: <CACMJSetObp0k312DmqhTCkw7jsf05OHX1yxbyYj+sVfbtwRcVQ@mail.gmail.com>

On 29/08/2023 15:24, Bartosz Golaszewski wrote:
>>> +phys_addr_t qcom_shm_bridge_to_phys_addr(void *vaddr)
>>> +{
>>> +     struct qcom_shm_bridge_chunk *chunk;
>>> +     struct qcom_shm_bridge_pool *pool;
>>> +
>>> +     guard(spinlock_irqsave)(&qcom_shm_bridge_chunks_lock);
>>> +
>>> +     chunk = radix_tree_lookup(&qcom_shm_bridge_chunks,
>>> +                               (unsigned long)vaddr);
>>> +     if (!chunk)
>>> +             return 0;
>>> +
>>> +     pool = chunk->parent;
>>> +
>>> +     guard(spinlock_irqsave)(&pool->lock);
>>
>> Why both locks are spinlocks? The locks are used quite a lot.
> 
> I'm not sure what to answer. The first one protects the global chunk
> mapping stored in the radix tree. The second one protects a single
> memory pool from concurrent access. Both can be modified from any
> context, hence spinlocks.

Not much PREEMPT friendly, although indeed protected code is small. At
least here, I did not check other places.

> 
>>
>>> +
>>> +     return gen_pool_virt_to_phys(pool->genpool, (unsigned long)vaddr);
>>> +}
>>> +EXPORT_SYMBOL_GPL(qcom_shm_bridge_to_phys_addr);
>>> +
>>> +static int qcom_shm_bridge_probe(struct platform_device *pdev)
>>> +{
>>> +     struct qcom_shm_bridge_pool *default_pool;
>>> +     struct device *dev = &pdev->dev;
>>> +     int ret;
>>> +
>>> +     /*
>>> +      * We need to wait for the SCM device to be created and bound to the
>>> +      * SCM driver.
>>> +      */
>>> +     if (!qcom_scm_is_available())
>>> +             return -EPROBE_DEFER;
>>
>> I think we miss here (and in all other drivers) device links to qcm.
>>
> 
> Well, SCM, once probed, cannot be unbound. What would device links
> guarantee above that?

Runtime PM, probe ordering (dependencies) detection.

> 
>>> +
>>> +     ret = qcom_scm_enable_shm_bridge();
>>> +     if (ret)
>>> +             return dev_err_probe(dev, ret,
>>> +                                  "Failed to enable the SHM bridge\n");
>>> +
>>> +     default_pool = qcom_shm_bridge_pool_new_for_dev(
>>> +                             dev, qcom_shm_bridge_default_pool_size);
>>> +     if (IS_ERR(default_pool))
>>> +             return dev_err_probe(dev, PTR_ERR(default_pool),
>>> +                                  "Failed to create the default SHM Bridge pool\n");
>>> +
>>> +     WRITE_ONCE(qcom_shm_bridge_default_pool, default_pool);
>>> +
>>> +     return 0;
>>> +}
>>> +
>>> +static const struct of_device_id qcom_shm_bridge_of_match[] = {
>>> +     { .compatible = "qcom,shm-bridge", },
>>> +     { }
>>> +};
>>> +
>>> +static struct platform_driver qcom_shm_bridge_driver = {
>>> +     .driver = {
>>> +             .name = "qcom-shm-bridge",
>>> +             .of_match_table = qcom_shm_bridge_of_match,
>>> +             /*
>>> +              * Once enabled, the SHM Bridge feature cannot be disabled so
>>> +              * there's no reason to ever unbind the driver.
>>> +              */
>>> +             .suppress_bind_attrs = true,
>>> +     },
>>> +     .probe = qcom_shm_bridge_probe,
>>> +};
>>> +
>>> +static int __init qcom_shm_bridge_init(void)
>>> +{
>>> +     return platform_driver_register(&qcom_shm_bridge_driver);
>>> +}
>>> +subsys_initcall(qcom_shm_bridge_init);
>>
>> Why this is part of subsystem? Should be rather device_initcall... or
>> simply module (and a tristate).
>>
> 
> We want it to get up as soon as possible (right after SCM, because SCM
> is the first user).

Then probably should be populated/spawned by SCM.

Best regards,
Krzysztof


  reply	other threads:[~2023-08-29 16:48 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-28 19:24 [PATCH 00/11] arm64: qcom: add and enable SHM Bridge support Bartosz Golaszewski
2023-08-28 19:24 ` [PATCH 01/11] firmware: qcom-scm: drop unneeded 'extern' specifiers Bartosz Golaszewski
2023-08-29  7:51   ` Krzysztof Kozlowski
2023-09-13 19:22   ` Bjorn Andersson
2023-08-28 19:24 ` [PATCH 02/11] firmware: qcom-scm: order includes alphabetically Bartosz Golaszewski
2023-08-29  7:52   ` Krzysztof Kozlowski
2023-08-28 19:24 ` [PATCH 03/11] firmware: qcom-scm: atomically assign and read the global __scm pointer Bartosz Golaszewski
2023-08-29  7:59   ` Krzysztof Kozlowski
2023-08-29 12:31     ` Bartosz Golaszewski
2023-08-29 12:48       ` Krzysztof Kozlowski
2023-10-17  8:24   ` Om Prakash Singh
2023-10-17  8:29     ` Bartosz Golaszewski
2023-08-28 19:25 ` [PATCH 04/11] firmware: qcom-scm: add support for SHM bridge operations Bartosz Golaszewski
2023-08-28 19:25 ` [PATCH 05/11] dt-bindings: document the Qualcomm TEE Shared Memory Bridge Bartosz Golaszewski
2023-08-29  8:02   ` Krzysztof Kozlowski
2023-08-29  9:30     ` Konrad Dybcio
2023-08-30 13:48       ` Bartosz Golaszewski
2023-08-30 14:31         ` Krzysztof Kozlowski
2023-08-30 14:39           ` Bartosz Golaszewski
2023-08-30 14:58             ` Krzysztof Kozlowski
2023-08-30 16:21               ` Bartosz Golaszewski
2023-08-28 19:25 ` [PATCH 06/11] firmware: qcom-shm-bridge: new driver Bartosz Golaszewski
2023-08-29  8:18   ` Krzysztof Kozlowski
2023-08-29 13:24     ` Bartosz Golaszewski
2023-08-29 16:47       ` Krzysztof Kozlowski [this message]
2023-08-30 13:09         ` Bartosz Golaszewski
2023-08-30 14:31           ` Krzysztof Kozlowski
2023-08-29  8:22   ` Krzysztof Kozlowski
2023-08-28 19:25 ` [PATCH 07/11] firmware: qcom-scm: use SHM bridge if available Bartosz Golaszewski
2023-08-29  5:32   ` kernel test robot
2023-08-29  5:43   ` kernel test robot
2023-08-28 19:25 ` [PATCH 08/11] arm64: defconfig: enable Qualcomm SHM bridge module Bartosz Golaszewski
2023-08-28 19:25 ` [PATCH 09/11] arm64: dts: qcom: sm8450: enable SHM bridge Bartosz Golaszewski
2023-08-28 19:25 ` [PATCH 10/11] arm64: dts: qcom: sa8775p: " Bartosz Golaszewski
2023-08-28 19:25 ` [PATCH 11/11] arm64: dts: qcom: sm8150: " Bartosz Golaszewski
2023-08-28 21:23 ` [PATCH 00/11] arm64: qcom: add and enable SHM Bridge support Dmitry Baryshkov
2023-08-29 19:03   ` Bartosz Golaszewski
2023-08-29 20:48     ` Dmitry Baryshkov
2023-09-14 19:36 ` (subset) " Bjorn Andersson

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