From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A91C33D1CB2; Thu, 14 May 2026 07:04:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778742297; cv=none; b=OeDZM8Y+/jUAcwb0SbNqFMgEvL0tJvWRQFdW+IOOFCMuDHx21YYrpFKdT/tTd7sfvlEGMHcK38Q8uV/TuF1xGuMnS896yU9KfoLvS7DT5QSwX5DTyzeanZeyVbgxyNBK4f3gNRHWTEbGhgK8HC0tnd15MTS0fGKyxa33c38V0Y4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778742297; c=relaxed/simple; bh=aPybIQGyqUA9qjM5+u2e5c6BwGWMHofN4WnuZwmO60o=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=o3kqaeZ9GkyoQBs3mgG2/McgfsSMHyHcUNoO1dUeVtTgUfNTGqIVXjWYcVRQkAFAHKk+pEGqfIwkVbuAlZpbeLdJ/MTjQlh6zy8GxAcH4X5XEV8TVw05COaQD/nL+S/2veqwheHv25kFAngTsHG/NladaSkE9EGFXlNdzSYV6oI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GDik+5nt; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GDik+5nt" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8A471C2BCB7; Thu, 14 May 2026 07:04:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778742297; bh=aPybIQGyqUA9qjM5+u2e5c6BwGWMHofN4WnuZwmO60o=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=GDik+5nteWXGocRGB0Pm8uCGUJSnN6oNc2y+F1YhavFhRTDEHthCx5trA99Mv3Jh+ vp1sRldEp+JZQJ6+7UKoz9qaT3zz32zDEeaS9Zk6GGWpuRdOiEIXW67Nqh1OezCDEW UDSIYfxPMiZeTX4uJin6ZrPGxikS4RqmOtEnBefA6oYRJnzpZBkuNbb6OkzglXyf2H U3DFkoKagI8hBJDAkOKQvNcr/3XbNhHgpQfYCnz1uFo3QmFdqabsODphhBSO6iQdlm 9nHHFuf8Csw3NdkJYrETQQh7LqGQwS0D7dLIJ3RCAVMqm7eOM2TlgTzbx4tCzjXmz4 0MwL1q+TRU7FA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wNQ7r-00000002GZR-1EXq; Thu, 14 May 2026 07:04:55 +0000 Date: Thu, 14 May 2026 08:04:54 +0100 Message-ID: <86bjeixyi1.wl-maz@kernel.org> From: Marc Zyngier To: Marek Vasut Cc: linux-arm-kernel@lists.infradead.org, Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Kuninori Morimoto , Magnus Damm , Rob Herring , devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: Re: [PATCH] arm64: dts: renesas: r8a78000: Fix GIC-720AE View 1 Redistributor description In-Reply-To: <20260513223125.43337-1-marek.vasut+renesas@mailbox.org> References: <20260513223125.43337-1-marek.vasut+renesas@mailbox.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: marek.vasut+renesas@mailbox.org, linux-arm-kernel@lists.infradead.org, conor+dt@kernel.org, geert+renesas@glider.be, krzk+dt@kernel.org, kuninori.morimoto.gx@renesas.com, magnus.damm@gmail.com, robh@kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Wed, 13 May 2026 23:30:08 +0100, Marek Vasut wrote: > > The Renesas R-Car X5H (R8A78000) SoC contains Arm CoreLink GIC-720AE > Generic Interrupt Controller with Multi View capability. Firmware has > access to configuration View 0, Linux kernel has access to View 1. Huh. That's pretty unexpected. The usual wisdom is to give the APs view 0 so that it looks like a "normal" machine, rather than only a partition of the system (which is what view != 0 indicates). I guess there is some additional fun going on there, such as other CPUs getting a portion of the GIC for themselves, and firmware preventing whatever is running on the APs to interact with them... > > The Arm CoreLink GIC-720AE Generic Interrupt Controller Technical > Reference Manual, currently latest r2p1 [1], chapter "Programmers model > for GIC-720AE", subchapter "Redistributor registers for control and > physical LPIs summary", part "GICR_TYPER, Redistributor Type Register" > clarifies register "GICR_TYPER" bit 4 "Last" behavior in Multi View > setup as follows: > > " > Last > Last Redistributor: > > 0 ... This Redistributor is not the last Redistributor on the chip. > 1 ... This Redistributor is the last Redistributor on the chip. > When GICD_CFGID.VIEW == 1, for views 1, 2, or 3 this bit > always returns 1. > " > > On this SoC, GICD_CFGID.VIEW is 1 and the Linux kernel has access to > View 1, therefore Linux kernel GICv3 driver will interpret register > "GICR_TYPER" bit 4 "Last" = 1 in the first Redistributor in continuous > Redistributor page as that first Redistributor being the one and only > Redistributor and will stop processing the continuous Redistributor > page further. This will prevent the other Redistributors from being > recognized by the system and used for other PEs. > > Because the hardware indicates that the continuous Redistributor page > is not continuous for View 1, 2, or 3, describe every Redistributor > separately in the DT. This makes all Redistributors for all cores > accessible in Linux. > > [1] https://developer.arm.com/documentation/102666/0201/Programmers-model-for-GIC-720AE/Redistributor-registers-for-control-and-physical-LPIs-summary/GICR-TYPER--Redistributor-Type-Register?lang=en > I am amazed that you managed to find anything at all on this web site. I would refrain from adding links to any ARM web sites in a commit message though. They tend to have a 10 minutes half-life period, and whole specs to disappear from public view when they are not flavour of the week anymore. A link to the equivalent PDF has better chances to survive further creative^WAI slop driven reorg of the documentation: https://documentation-service.arm.com/static/69ef3c1cd35efd294e335c43 but your best bet is to download it, archive it, and refer to it yourself. > Fixes: 63500d12cf76 ("arm64: dts: renesas: Add R8A78000 SoC support") > Signed-off-by: Marek Vasut Acked-by: Marc Zyngier M. -- Without deviation from the norm, progress is not possible.