From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4998B1EBA19; Fri, 21 Mar 2025 09:04:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742547844; cv=none; b=gsM98J52J9S0vAtxMZWtLexNlp29ogjrrw12xFCy6LmyeKZEAHLRvFEWPbUfCeQJC98K7SR2kGoXjEaitnAmMm+wMy86P0Z4CmPn6ajXOjg8jRLjvsL+jDd0jDISNGnaZ4dF6JxUx+6zOwps4L2G8R1byLJbQKWpX32L0e0vRQs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742547844; c=relaxed/simple; bh=8fw7paiuFxV9WqkArmDeFOzxQ4fMfuMVsbglLpRjvSo=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=CkHSFphA/jqBZroezoWJJ/BCDeh08+vgAs3z1aD1c2InZY/e6SnJB0A/AzHH5DYz5j30S3W7PZ5qBU/UKMRNpxPeqnYJfpGDEM8vg9ITVWYgm7ZRxYOXOlVqIg2PdTjHtWGgbomVZL57fbNHMKi+kKgVh6ZyMbRWuzZjB2OFTEY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uruPfbQ6; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uruPfbQ6" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B8B21C4CEE3; Fri, 21 Mar 2025 09:04:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1742547843; bh=8fw7paiuFxV9WqkArmDeFOzxQ4fMfuMVsbglLpRjvSo=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=uruPfbQ6Ibea2mcVkJwvG/qhmgSuVdvzisdlkwMcKGC6hKlt2si1BaTJeTK/6OlVB m28GTejQo3TqU+reqVJGB7NYZ/HF51FLsC6k8l1eaLdNZ3oPqU2Ji37CXJdLQQrzyf lREvAcAzWY0o6zRbRD2UlYTM6as5feGd/FZn5G6QGoD1KbbPDikWgEKGOpZ9kgEnjg t+SPN0fyj9SPehxUYikwQLWJvoCXfpQ0vTlCY/ICEdSZlxUmv/sFLdV+MBwDY12iZi E2KIvhPfxNikwT8MDC+7KnWnrS74YA7y3Vp+2ubZQh17Ijf2GPZV3qjFmomUbZXnat pZVhQx2PJ30SQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tvYIL-00FiXX-DQ; Fri, 21 Mar 2025 09:04:01 +0000 Date: Fri, 21 Mar 2025 09:04:00 +0000 Message-ID: <86bjtun4an.wl-maz@kernel.org> From: Marc Zyngier To: Peter Chen Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, marcin@juszkiewicz.com.pl, Krzysztof Kozlowski , Fugang Duan Subject: Re: [PATCH v4 5/6] arm64: dts: cix: add initial CIX P1(SKY1) dts support In-Reply-To: References: <20250305053823.2048217-1-peter.chen@cixtech.com> <20250305053823.2048217-6-peter.chen@cixtech.com> <86frj8m4be.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: peter.chen@cixtech.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, marcin@juszkiewicz.com.pl, krzysztof.kozlowski@linaro.org, fugang.duan@cixtech.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 20 Mar 2025 09:57:13 +0000, Peter Chen wrote: > > On 25-03-20 09:36:37, Marc Zyngier wrote: > > Peter Chen wrote: > > > > > > + pmu-a520 { > > > + compatible = "arm,cortex-a520-pmu"; > > > + interrupts = ; > > > + }; > > > + > > > + pmu-a720 { > > > + compatible = "arm,cortex-a720-pmu"; > > > + interrupts = ; > > > + }; > > > + > > > + pmu-spe { > > > + compatible = "arm,statistical-profiling-extension-v1"; > > > + interrupts = ; > > > + }; > > > > SPE should follow the same model as the PMU, as each CPU has its own > > SPE implementation, exposing different micro-architectural details. > > > > Hi Marc, > > Thanks for your reply. But there is only one compatible string > "statistical-profiling-extension-v1" at drivers/perf/arm_spe_pmu.c, > how could differentiate pmu-spe-a720 and pmu-spe-a520, do I need > to change arm_spe_pmu.c as well? I don't think there is a need to have different compatible. The driver can probe which CPU this is on, and work out the implemented subfeatures from the PMSIDR_EL1 register. New compatible strings are better avoided when there is a way to probe/discover the HW (and in most cases, there is). Note that this equally applies to TRBE, which also explicitly deals with interrupt partitioning and yet only has a single compatible. Please consider adding TRBE support when you repost this series. Thanks, M. -- Without deviation from the norm, progress is not possible.