From: Matthias Brugger <matthias.bgg@gmail.com>
To: Moudy Ho <moudy.ho@mediatek.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Hans Verkuil <hverkuil-cisco@xs4all.nl>
Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Rob Landley <rob@landley.net>,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
Alexandre Courbot <acourbot@chromium.org>,
tfiga@chromium.org, drinkcat@chromium.org, pihsun@chromium.org,
hsinyi@google.com,
Benjamin Gaignard <benjamin.gaignard@collabora.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
daoyuan huang <daoyuan.huang@mediatek.com>,
Ping-Hsun Wu <ping-hsun.wu@mediatek.com>,
allen-kh.cheng@mediatek.com, xiandong.wang@mediatek.com,
randy.wu@mediatek.com, jason-jh.lin@mediatek.com,
roy-cw.yeh@mediatek.com, river.cheng@mediatek.com,
Project_Global_Chrome_Upstream_Group@mediatek.com,
cellopoint.kai@gmail.com
Subject: Re: [PATCH v18 3/4] dts: arm64: mt8183: add Mediatek MDP3 nodes
Date: Tue, 14 Jun 2022 17:09:09 +0200 [thread overview]
Message-ID: <86c40dc9-c48a-4f42-88ea-7a91b5bb425a@gmail.com> (raw)
In-Reply-To: <20220610064504.8302-4-moudy.ho@mediatek.com>
On 10/06/2022 08:45, Moudy Ho wrote:
> Add device nodes for Media Data Path 3 (MDP3) modules.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Looks good to me. I'm ready to take this as soon as 1,2 and 4 got merged.
Matthias
> ---
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 79 +++++++++++++++++++++++-
> 1 file changed, 78 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index e74fd253478b..ade5997a9656 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -1389,6 +1389,50 @@
> mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> };
>
> + mdp3-rdma0@14001000 {
> + compatible = "mediatek,mt8183-mdp3-rdma";
> + reg = <0 0x14001000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_MDP_RDMA0>,
> + <&mmsys CLK_MM_MDP_RSZ1>;
> + iommus = <&iommu M4U_PORT_MDP_RDMA0>;
> + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
> + <&gce 21 CMDQ_THR_PRIO_LOWEST 0>;
> + };
> +
> + mdp3-rsz0@14003000 {
> + compatible = "mediatek,mt8183-mdp3-rsz";
> + reg = <0 0x14003000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_RSZ0>;
> + };
> +
> + mdp3-rsz1@14004000 {
> + compatible = "mediatek,mt8183-mdp3-rsz";
> + reg = <0 0x14004000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_RSZ1>;
> + };
> +
> + mdp3-wrot0@14005000 {
> + compatible = "mediatek,mt8183-mdp3-wrot";
> + reg = <0 0x14005000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_MDP_WROT0>;
> + iommus = <&iommu M4U_PORT_MDP_WROT0>;
> + };
> +
> + mdp3-wdma@14006000 {
> + compatible = "mediatek,mt8183-mdp3-wdma";
> + reg = <0 0x14006000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_MDP_WDMA0>;
> + iommus = <&iommu M4U_PORT_MDP_WDMA0>;
> + };
> +
> ovl0: ovl@14008000 {
> compatible = "mediatek,mt8183-disp-ovl";
> reg = <0 0x14008000 0 0x1000>;
> @@ -1507,7 +1551,33 @@
> interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
> - <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
> + <CMDQ_EVENT_MUTEX_STREAM_DONE1>,
> + <CMDQ_EVENT_MDP_RDMA0_SOF>,
> + <CMDQ_EVENT_MDP_RDMA0_EOF>,
> + <CMDQ_EVENT_MDP_RSZ0_SOF>,
> + <CMDQ_EVENT_MDP_RSZ1_SOF>,
> + <CMDQ_EVENT_MDP_TDSHP_SOF>,
> + <CMDQ_EVENT_MDP_WROT0_SOF>,
> + <CMDQ_EVENT_MDP_WROT0_EOF>,
> + <CMDQ_EVENT_MDP_WDMA0_SOF>,
> + <CMDQ_EVENT_MDP_WDMA0_EOF>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_0>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_1>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_2>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_3>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_4>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_5>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_6>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_7>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_8>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_9>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_10>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_11>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_12>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_13>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_14>,
> + <CMDQ_EVENT_WPE_A_DONE>,
> + <CMDQ_EVENT_SPE_B_DONE>;
> mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
> };
>
> @@ -1532,6 +1602,13 @@
> power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> };
>
> + mdp3-ccorr@1401c000 {
> + compatible = "mediatek,mt8183-mdp3-ccorr";
> + reg = <0 0x1401c000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_CCORR>;
> + };
> +
> imgsys: syscon@15020000 {
> compatible = "mediatek,mt8183-imgsys", "syscon";
> reg = <0 0x15020000 0 0x1000>;
next prev parent reply other threads:[~2022-06-14 15:09 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-10 6:45 [PATCH v18 0/4] media: mediatek: support mdp3 on mt8183 platform Moudy Ho
2022-06-10 6:45 ` [PATCH v18 1/4] dt-binding: mediatek: add bindings for MediaTek MDP3 components Moudy Ho
2022-06-10 6:45 ` [PATCH v18 2/4] dt-binding: mediatek: add bindings for MediaTek CCORR and WDMA Moudy Ho
2022-06-10 6:45 ` [PATCH v18 3/4] dts: arm64: mt8183: add Mediatek MDP3 nodes Moudy Ho
2022-06-13 10:59 ` AngeloGioacchino Del Regno
2022-06-14 15:09 ` Matthias Brugger [this message]
2022-06-10 6:45 ` [PATCH v18 4/4] media: platform: mtk-mdp3: add Mediatek MDP3 driver Moudy Ho
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