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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id my16-20020a1709065a5000b006fecf74395bsm1985821ejc.8.2022.06.02.11.37.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 Jun 2022 11:37:01 -0700 (PDT) Message-ID: <86ca80e4-b0de-4a83-f69e-5d15dc16584f@linaro.org> Date: Thu, 2 Jun 2022 20:37:00 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH v2] arm64: dts: Add support for Stratix 10 Software Virtual Platform Content-Language: en-US To: wen.ping.teh@intel.com, Catalin Marinas , Will Deacon , Dinh Nguyen , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20220602141151.3431212-1-wen.ping.teh@intel.com> From: Krzysztof Kozlowski In-Reply-To: <20220602141151.3431212-1-wen.ping.teh@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 02/06/2022 16:11, wen.ping.teh@intel.com wrote: > From: Teh Wen Ping > > Add Stratix 10 Software Virtual Platform device tree > > Signed-off-by: Teh Wen Ping > --- > > changes in v2: > -remove indentation before GPL > -change root compatible to "altr,socfpga-stratix10" > -remove bootargs > -move clock-frequency to label > -remove l2-cache > -remove no longer exist authors from commit message > > arch/arm64/Kconfig.platforms | 3 +- > arch/arm64/boot/dts/altera/Makefile | 3 +- > .../dts/altera/socfpga_stratix10_swvp.dts | 117 ++++++++++++++++++ > 3 files changed, 121 insertions(+), 2 deletions(-) > create mode 100644 arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts > > diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms > index de9a18d3026f..48abe5dafaae 100644 > --- a/arch/arm64/Kconfig.platforms > +++ b/arch/arm64/Kconfig.platforms > @@ -249,7 +249,8 @@ config ARCH_INTEL_SOCFPGA > bool "Intel's SoCFPGA ARMv8 Families" > help > This enables support for Intel's SoCFPGA ARMv8 families: > - Stratix 10 (ex. Altera), Agilex and eASIC N5X. > + Stratix 10 (ex. Altera), Stratix10 Software Virtual Platform, > + Agilex and eASIC N5X. > > config ARCH_SYNQUACER > bool "Socionext SynQuacer SoC Family" > diff --git a/arch/arm64/boot/dts/altera/Makefile b/arch/arm64/boot/dts/altera/Makefile > index 4db83fbeb115..1bf0c472f6b4 100644 > --- a/arch/arm64/boot/dts/altera/Makefile > +++ b/arch/arm64/boot/dts/altera/Makefile > @@ -1,3 +1,4 @@ > # SPDX-License-Identifier: GPL-2.0-only > dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_stratix10_socdk.dtb \ > - socfpga_stratix10_socdk_nand.dtb > + socfpga_stratix10_socdk_nand.dtb \ > + socfpga_stratix10_swvp.dtb > diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts > new file mode 100644 > index 000000000000..93fa5091a6c3 > --- /dev/null > +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts > @@ -0,0 +1,117 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2022, Intel Corporation > + */ > + > +#include "socfpga_stratix10.dtsi" > + > +/ { > + model = "SOCFPGA Stratix 10 SWVP"; > + compatible = "altr,socfpga-stratix10"; You cannot use someone else's compatible. You need your own and then also you need to document it. Check existing sources for examples. Documentation/devicetree/bindings/arm/altera.yaml > + > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + > + timer0 = &timer0; > + timer1 = &timer1; > + timer2 = &timer2; > + timer3 = &timer3; > + > + ethernet0 = &gmac0; > + ethernet1 = &gmac1; > + ethernet2 = &gmac2; > + }; > + > + chosen { > + stdout-path = "serial1:115200n8"; > + linux,initrd-start = <0x10000000>; > + linux,initrd-end = <0x125c8324>; Best regards, Krzysztof