From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51EF5C4332F for ; Fri, 9 Dec 2022 12:02:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229769AbiLIMCF (ORCPT ); Fri, 9 Dec 2022 07:02:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37900 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230057AbiLIMBf (ORCPT ); Fri, 9 Dec 2022 07:01:35 -0500 Received: from sin.source.kernel.org (sin.source.kernel.org [145.40.73.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5136F6ACD6; Fri, 9 Dec 2022 04:01:28 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id A5B85CE2969; Fri, 9 Dec 2022 12:01:26 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8C602C433D2; Fri, 9 Dec 2022 12:01:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1670587284; bh=VO1jn+Chl+xyrflXzrrO7caYAzOuX+cY2t9eRqjN5PM=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=P6bvHrBh70ZZ8nZBuZs/yt+uDSQokcyK+zE2Txngfcuzobdrka6BLdoHI+V9AyL+0 jSNbqFg8o3Mrza1I/hWMGbEUPpRp4TRTuRXhQkhI9JQN4omF0I2mn2LG7p0B8fK2Ec OdN558i7eUDxEEunzTacG+Z/ykbzqhrq36jgg3MnnwH5UqqLqG6KFHhgdg9NQMpsgu PcBmCxLe4VMocyLI6vfRSjEoHela7dxY0JOBITItpXL2EiqirP5u/BSAbwEWXRwpTd yn1p3MW//Oo6E35jECYxEP256TUdcs+N0Vn+Sh3h2JETsTN1bzgM7WmD5oh9F3q42W DZzHm2uPIxHEg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1p3c4A-00BaAw-52; Fri, 09 Dec 2022 12:01:22 +0000 Date: Fri, 09 Dec 2022 12:01:21 +0000 Message-ID: <86cz8srdke.wl-maz@kernel.org> From: Marc Zyngier To: Sebastian Reichel , Kever Yang Cc: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Linus Walleij , Christopher Obbard , Benjamin Gaignard , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Yifeng Zhao , Elaine Zhang , Sugar Zhang Subject: Re: [PATCHv5 3/7] arm64: dts: rockchip: Add base DT for rk3588 SoC In-Reply-To: <20221205172350.75234-4-sebastian.reichel@collabora.com> References: <20221205172350.75234-1-sebastian.reichel@collabora.com> <20221205172350.75234-4-sebastian.reichel@collabora.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: sebastian.reichel@collabora.com, kever.yang@rock-chips.com, heiko@sntech.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linus.walleij@linaro.org, chris.obbard@collabora.com, benjamin.gaignard@collabora.com, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@collabora.com, yifeng.zhao@rock-chips.com, zhangqing@rock-chips.com, sugar.zhang@rock-chips.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, 05 Dec 2022 17:23:46 +0000, Sebastian Reichel wrote: > > From: Kever Yang > > This initial version supports (single core) CPU, dma, interrupts, timers, > UART and SDHCI. In short - everything necessary to boot Linux on this > system on chip. > > The DT is split into rk3588 and rk3588s, which is a reduced version > (i.e. with less peripherals) of the former. > > Signed-off-by: Yifeng Zhao > Signed-off-by: Elaine Zhang > Signed-off-by: Sugar Zhang > Signed-off-by: Kever Yang > [rebase, squash and reword commit message] > Signed-off-by: Sebastian Reichel > --- > arch/arm64/boot/dts/rockchip/rk3588.dtsi | 58 + > arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1672 +++++++++++++++++++++ > 2 files changed, 1730 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk3588.dtsi > create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s.dtsi > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi > new file mode 100644 > index 000000000000..ecdd2294cd42 > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi > @@ -0,0 +1,1672 @@ [...] > + pmu-a55 { > + compatible = "arm,cortex-a55-pmu"; > + interrupts = ; > + }; > + > + pmu-a76 { > + compatible = "arm,cortex-a76-pmu"; > + interrupts = ; > + }; Two PMUs with the same PPI and no partition? This is totally wrong. Please see how RK3399 does it, with each PMU having a PPI partition allocated. See the PMU binding for the details. > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + spll: clock-0 { > + compatible = "fixed-clock"; > + clock-frequency = <702000000>; > + clock-output-names = "spll"; > + #clock-cells = <0>; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = , > + , > + , > + ; You have a set of ARMv8.2 cores, which do have an interrupt for the EL2 virtual timer. Please add this interrupt and while you're at it, add the interrupt-names properties that are associated with them. See the binding for the details. [...] > + gic: interrupt-controller@fe600000 { > + compatible = "arm,gic-v3"; > + reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ > + <0x0 0xfe680000 0 0x100000>; /* GICR */ > + interrupts = ; > + interrupt-controller; > + mbi-alias = <0x0 0xfe610000>; > + mbi-ranges = <424 56>; > + msi-controller; > + #interrupt-cells = <3>; > + > + ppi-partitions { > + interrupt-partition-0 { > + affinity = < > + &cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3 > + &cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3 > + >; > + }; > + }; What is the purpose of having an interrupt partition that covers *all* the CPUs? This makes zero sense. You need to: - Bump #interrupt-cells to 4, as per the GIC binding - Create PPI partitions to segregate the two CPU types - Make the PMU devices use the corresponding PPI partition as per the binding - Fix all the interrupt specifiers to use 4 cells instead of 3 Again, RK3399 got it right, and for once I'm advocating some sort of copy/paste... M. -- Without deviation from the norm, progress is not possible.