From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E73A28152A; Tue, 6 May 2025 14:05:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746540343; cv=none; b=V5gZSO96cZGoWVROpo9JP1thkmKbFsOZYkTKldjOh9AnJ2IhWNNDMPY0wKfrGYR/LlEKz7ChQxX+GAGSHgIaTxqEdhc8oc8j87pAnuX4XJ36iSCzyIrJNJ6ieIoX7CRJ0q29TtGIL8i/RE+0sjP+YCpqjfru5/ye8rDVEEcnSMw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746540343; c=relaxed/simple; bh=lwRmuP2GMcWJ8L+R/b+kXBU7HZjwjH6hqn/r0N3fvZM=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=hWVNIuIF3z/o0cjRrSU0YwbV7jO7cUGk9/MYSAEvp5p3VSuMidEBTin2UaE7tPAkKJyKJsqEu87Wwn1h1vQq8gv0OYbYAngziazEXru8Zr0in4jPQGSipIPAsu2k42iiCI/x31SxM/V+f2i42tis1HMb/Ze9cJVTAcChk/oRM1E= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=EvKnN4Uc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EvKnN4Uc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CD6D5C4CEE4; Tue, 6 May 2025 14:05:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746540342; bh=lwRmuP2GMcWJ8L+R/b+kXBU7HZjwjH6hqn/r0N3fvZM=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=EvKnN4Ucmz+o7iRTO0Gy4X3NDy0tma/vf8EnkOdVJNlA7iglaUg3TUPnQei1OhhbP IbxjATWMkyzzU4c9/z1xRjR8gGDTT2qYC6IKzc5+/TbAkzLFkMngjvsCMsAn4ihQWe twvGJvWCL1NiSYBjT32Ip/Lbl9tJBFymL0mjTlxIDBwKbuBPz9VJQqLZGfkuNtpgGw BVZvxElF6fzJYdRN+gRXUkdCMYdCPoGtQ9fgZgkmaVFnuUnJcZj36y/lJoXxycqwCO 9rO92UbnTDUbd5f58F6hnaNEHVQU0Y0DJXi5AAB33xvbHlWwwd2ip433GQKpEBvNQt kmL7ZtOzL8GXQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uCIvU-00CGRv-QZ; Tue, 06 May 2025 15:05:40 +0100 Date: Tue, 06 May 2025 15:05:39 +0100 Message-ID: <86frhhhm18.wl-maz@kernel.org> From: Marc Zyngier To: Lorenzo Pieralisi Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , Jiri Slaby , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v3 00/25] Arm GICv5: Host driver implementation In-Reply-To: <20250506-gicv5-host-v3-0-6edd5a92fd09@kernel.org> References: <20250506-gicv5-host-v3-0-6edd5a92fd09@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: lpieralisi@kernel.org, tglx@linutronix.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, sascha.bischoff@arm.com, timothy.hayes@arm.com, Liam.Howlett@oracle.com, mark.rutland@arm.com, jirislaby@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 06 May 2025 13:23:29 +0100, Lorenzo Pieralisi wrote: > > ============= > 2.5 GICv5 IWB > ============= > > The IWB driver has been dropped owing to issues encountered with > core code DOMAIN_BUS_WIRED_TO_MSI bus token handling: > > https://lore.kernel.org/lkml/87tt6310hu.wl-maz@kernel.org/ This problem does not have much to do with DOMAIN_BUS_WIRED_TO_MSI. The issues are that: - the core code calls into the .prepare domain on a per-interrupt basis instead of on a per *device* basis. This is a complete violation of the MSI API, because .prepare is when you are supposed to perform resource reservation (in the GICv3 parlance, that's ITT allocation + MAPD command). - the same function calls .prepare for a *single* interrupt, effectively telling the irqchip "my device has only one interrupt". Because I'm super generous (and don't like wasting precious bytes), I allocate 32 LPIs at the minimum. Only snag is that I could do with 300+ interrupts, and calling repeatedly doesn't help at all, since we cannot *grow* an ITT. So this code needs to be taken to the backyard and beaten into shape before we can make use of it. My D05 (with its collection of MBIGENs) only works by accident at the moment, as I found out yesterday, and GICv5 IWB is in the same boat, since it reuses the msi-parent thing, and therefore the same heuristic. I guess not having the IWB immediately isn't too big a deal, but I really didn't expect to find this... Thanks, M. -- Without deviation from the norm, progress is not possible.