From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58176222582; Thu, 20 Mar 2025 09:36:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742463400; cv=none; b=tNfI41+NK4xsm6ItvqguMP5y6NjeQGGtIztPrBkaQlQlN2Rel8fH7PNjsitnmeRtWXgVQU4MKxhLTebdsiYZAknfawEzaYwTBjfRgJc6JCKE5yH0UQGOJQ8tr+mYldIgPo3Y3Yb2INrEWgf76lR7T8LrVjpW1TXwxOdhhUhJAyM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742463400; c=relaxed/simple; bh=rmeSFUps1Kb2AtfHcDE+ZMpy59r9/O2cRtKHsWdcCUk=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=eBqGUwljuXwipW9kku5yY1gHNDxhUoMlL8tdCM41v3qQCwLK59i+OQHgQgO16qiI84TE7kUPndfSbOie6XxpvQRCK4+gaXx/avi3vCYCgNNRAnCvRgokF+S+Lp2dfaTlwbenQPU6bhJtO9kaIFaKcB8pq5aXsR0cf+bipfCjyfg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tp7QHmDH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tp7QHmDH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BD713C4CEE8; Thu, 20 Mar 2025 09:36:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1742463399; bh=rmeSFUps1Kb2AtfHcDE+ZMpy59r9/O2cRtKHsWdcCUk=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=tp7QHmDHLsCLToRlVqIsxUleoMkwXDIZ4bPn9UQusiIXJOJMwUPHiWRS+gq7o8MOf IrblgrUP3CzOiWTL1R6GlxU1uzYrvqR4Ozr29XyCknH5ld1l8PjdG+RV1VdRsAgnis /QP8mAM0Y3mMfX1FWYG6PtgsbQfYEXzRc+kG3bVi6VkbTK3v/GIW6u98dPVvgCGcC/ ATWGz4B6i4ZxUF9tzvWMY5KKKCN5TCOTosnihTzXzoQ4UXJzjVVHVtNHQz5qMMJP6B QTGuTwiPDew5odbN7r0OQsa8RdFysk2x6w/Zdkc1fvIy4PKTcx0V2flwwWSbc0JhCE /RnpJ/E0H/0cw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tvCKL-00FMtF-K5; Thu, 20 Mar 2025 09:36:37 +0000 Date: Thu, 20 Mar 2025 09:36:37 +0000 Message-ID: <86frj8m4be.wl-maz@kernel.org> From: Marc Zyngier To: Peter Chen Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, marcin@juszkiewicz.com.pl, Krzysztof Kozlowski , Fugang Duan Subject: Re: [PATCH v4 5/6] arm64: dts: cix: add initial CIX P1(SKY1) dts support In-Reply-To: <20250305053823.2048217-6-peter.chen@cixtech.com> References: <20250305053823.2048217-1-peter.chen@cixtech.com> <20250305053823.2048217-6-peter.chen@cixtech.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: peter.chen@cixtech.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, marcin@juszkiewicz.com.pl, krzysztof.kozlowski@linaro.org, fugang.duan@cixtech.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Wed, 05 Mar 2025 05:38:22 +0000, Peter Chen wrote: > > + pmu-a520 { > + compatible = "arm,cortex-a520-pmu"; > + interrupts = ; > + }; > + > + pmu-a720 { > + compatible = "arm,cortex-a720-pmu"; > + interrupts = ; > + }; > + > + pmu-spe { > + compatible = "arm,statistical-profiling-extension-v1"; > + interrupts = ; > + }; SPE should follow the same model as the PMU, as each CPU has its own SPE implementation, exposing different micro-architectural details. The rest looks OK. M. -- Without deviation from the norm, progress is not possible.