From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marc Zyngier Subject: Re: [RFC 0/2] Add workaround for core wake-up on IPI for i.MX8MQ Date: Wed, 12 Jun 2019 08:35:41 +0100 Message-ID: <86ftofgss2.wl-marc.zyngier@arm.com> References: <20190610121346.15779-1-abel.vesa@nxp.com> <20190610131921.GB14647@lakrids.cambridge.arm.com> <20190610132910.srd4j2gtidjeppdx@fsr-ub1664-175> <6f1052ea-623a-b2e8-9aa8-22aef5fab4ca@arm.com> <20190610135514.xd5myavjsloos2y3@fsr-ub1664-175> <7b86aa90-6d64-589c-f11e-d2ee6ab3fd54@arm.com> Mime-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Thomas Gleixner Cc: Mark Rutland , "devicetree@vger.kernel.org" , Lorenzo Pieralisi , Abel Vesa , Carlo Caione , Fabio Estevam , Sascha Hauer , "linux-kernel@vger.kernel.org" , Rob Herring , Jacky Bai , dl-linux-imx , Pengutronix Kernel Team , Abel Vesa , Leonard Crestez , Shawn Guo , "linux-arm-kernel@lists.infradead.org" , Lucas Stach List-Id: devicetree@vger.kernel.org On Wed, 12 Jun 2019 08:14:16 +0100, Thomas Gleixner wrote: > On Mon, 10 Jun 2019, Leonard Crestez wrote: > > On 6/10/2019 5:08 PM, Marc Zyngier wrote: > > > Nobody is talking about performance here. It is strictly about > > > correctness, and what I read about this system is that it cannot > > > reliably use cpuidle. > > My argument was that it's fine if PPIs and LPIs are broken as long as > > they're not used: > > > > * PPIs are only used for local timer which is not used for wakeup. > > Huch? The timer has to bring the CPU out of idle as any other > interrupt. They use a separate hack for that, pretending that the timer is stopped during idle (it isn't), and setup a broadcast timer when entering idle. That timer uses an interrupt that can wake-up the target CPU, and all is well in the world. Sort of. Of course, this breaks as PPIs are not only used by the timer, but also by a number of other HW bits (PMU, GIC, guest and hypervisor timers), and they don't have corresponding hacks to back them up. Thanks, M. -- Jazz is not dead, it just smells funny.