From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CA0621ABD4; Tue, 8 Jul 2025 18:18:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751998690; cv=none; b=AUq3AHR4woo56eLktv4zIvHkIEaHAPDpEadiuOg7J7yxKtARdmDWyEwQAZIEGthLsytJ8vP27c3GHktpQaEOcL3DF19gRn/0g4YF8Ylrv4EDmE/AjP138q3QDwF3Slo7YR7n1hLBAb8kFlvwl+TE0RDaU4ahjbv9dwwdr1ePPZk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751998690; c=relaxed/simple; bh=PKu6/ThVozLLn7QVgY0cNBC72u37vzczW0XG6NNicpg=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=YuPQ3KsdoIvkc2IIGLPGUcIqf1n5coIRVD5Z4MVyAydrRfVWaYcnh8/qChWrRz2Au3Ssk3IaQqd5dTda0EoFbIas+LS+QcPh9vriaoB9ztB2Qbf8cUbzNSXFfhe06oLsnxQQYee6fJIepZgdZbF1fvGISxYx5Et8NZfwM1YWMVM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZgBt4z/G; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZgBt4z/G" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9E936C4CEED; Tue, 8 Jul 2025 18:18:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751998689; bh=PKu6/ThVozLLn7QVgY0cNBC72u37vzczW0XG6NNicpg=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=ZgBt4z/GsgkccT31iLNkliSi4hbeCcwskRE2LCNvIscD0JNwyrcnPqREmog8m8eoZ 9H/qk0MrBkhHBfgc86BKsWc9qzFeoHG0Apx1vExK2mJlewaBFFvh1zexoB+kVRL/bd cBQzlpKNXa/ao9V+3iWi7CT0uPVf657ze14JhIr0DYg8pJDeVMTpoVSn8SX6KCb8Et a5HuvvD2iWSBYVjA1UMWo8jB4oRhv7u5graujTyoR+kZXwtuciBUykYw9737QJpXcO jsQa93xKez07Z73M8PFvAkI2tP6tc1h6BBcHd3xOYKk+u+hPc609EtLd0UllqPbFBg zp67BrGbMkOnw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uZCtK-00DrVr-N7; Tue, 08 Jul 2025 19:18:07 +0100 Date: Tue, 08 Jul 2025 19:18:06 +0100 Message-ID: <86ms9ea6n5.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton , Lorenzo Pieralisi Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Arnd Bergmann , Sascha Bischoff , Jonathan Cameron , Timothy Hayes , Bjorn Helgaas , "Liam R. Howlett" , Peter Maydell , Mark Rutland , Jiri Slaby , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH v7 00/31] Arm GICv5: Host driver implementation In-Reply-To: <20250703-gicv5-host-v7-0-12e71f1b3528@kernel.org> References: <20250703-gicv5-host-v7-0-12e71f1b3528@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oliver.upton@linux.dev, lpieralisi@kernel.org, tglx@linutronix.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, sascha.bischoff@arm.com, Jonathan.Cameron@huawei.com, timothy.hayes@arm.com, bhelgaas@google.com, Liam.Howlett@oracle.com, peter.maydell@linaro.org, mark.rutland@arm.com, jirislaby@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 03 Jul 2025 11:24:50 +0100, Lorenzo Pieralisi wrote: > > Implement the irqchip kernel driver for the Arm GICv5 architecture, > as described in the GICv5 beta0 specification, available at: > > https://developer.arm.com/documentation/aes0070 > > The GICv5 architecture is composed of multiple components: > > - one or more IRS (Interrupt Routing Service) > - zero or more ITS (Interrupt Translation Service) > - zero or more IWB (Interrupt Wire Bridge) > > The GICv5 host kernel driver is organized into units corresponding > to GICv5 components. > > The GICv5 architecture defines the following interrupt types: > > - PPI (PE-Private Peripheral Interrupt) > - SPI (Shared Peripheral Interrupt) > - LPI (Logical Peripheral Interrupt) > > This series adds sysreg entries required to automatically generate > GICv5 registers handling code, one patch per-register. > > This patch series is split into patches matching *logical* entities, > to make the review easier. [...] Oliver, I've pushed out a branch with these patches at [1]. Could you please stash it in kvmarm/next and add the KVM bits to it so that it can all simmer in -next for a bit? Thanks, M. [1] git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git gic-v5-host -- Without deviation from the norm, progress is not possible.