From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FB13AD24; Thu, 1 May 2025 14:32:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746109973; cv=none; b=IDeAECUeCkR2TsFcEYcWkfoZfx6uYihZj0o3JblaqQ+Y1+Lw07252SktoHmayEJy1Pt3T7ZLQNewfsUsKr4qAQ9pKuipZ8fpOSjP4/TEvnst6mUNye5DTUMwpfk4Qtf+V2gfKMX0B4Q61hSMzljE1CPA+mgqmWS8gHZKgajbg+k= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746109973; c=relaxed/simple; bh=ChU0LnGye3/sKTfBYj0v3uZsJYxV4lwJzxdMPJHVNdw=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=ugq9vn3t4VuF6q1VOqL+IHJL0bKa/G1VtbFyNaWDhrKLk49TKiYeWZOz835Wve0MZOcIBs978tmZF2PaSaUNWJW1/kIcJOD1AlPjXnjaBtHZW6Ti78oseqLqOoBKMD2cbwNc+V1AtQ5/PcDk00jfUFZXPkyEX7skn4ylWYKq0Hk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tzdD4tdW; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tzdD4tdW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EC572C4CEE3; Thu, 1 May 2025 14:32:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746109973; bh=ChU0LnGye3/sKTfBYj0v3uZsJYxV4lwJzxdMPJHVNdw=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=tzdD4tdWov6bTcHQjRH/3i/YplItQFfWojku1jIYAZEPAeyKWG/GlIwYUo0D3OmEn omyuAVWcjzTzM8/a3GEeToqhJkb2pUPjnOohvN5NHlrV+CWtW2EsfQzySMbqfH/E2M Ft0wYaR2a7NxL3Kw9kz6fYk8ArNGAuMMgEYJ6BKelaKjM8jGOYrqyoSH8EN+B/loLb vzLdYLMhlgPYuWkMAKbraZLtYbWhtiphlnphtBOCTdzas37rkhi2ZqB7/l1mfKh6sI qBS7FkmuwjN66QAbvL1s74uaz/tuOnKqbZ++h9f2klvBBncgNG7GrGWquGsGxfj5Vu q+0lsmAfC5/Qw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uAUy3-00AbJY-00; Thu, 01 May 2025 15:32:51 +0100 Date: Thu, 01 May 2025 15:32:49 +0100 Message-ID: <86seloh04u.wl-maz@kernel.org> From: Marc Zyngier To: Lorenzo Pieralisi Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 15/22] arm64: Disable GICv5 read/write/instruction traps In-Reply-To: <20250424-gicv5-host-v2-15-545edcaf012b@kernel.org> References: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> <20250424-gicv5-host-v2-15-545edcaf012b@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: lpieralisi@kernel.org, tglx@linutronix.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, sascha.bischoff@arm.com, timothy.hayes@arm.com, Liam.Howlett@oracle.com, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 24 Apr 2025 11:25:26 +0100, Lorenzo Pieralisi wrote: > > GICv5 trap configuration registers value is UNKNOWN at reset. > > Initialize GICv5 EL2 trap configuration registers to prevent > trapping GICv5 instruction/register access upon entering the > kernel. > > Signed-off-by: Lorenzo Pieralisi > Cc: Will Deacon > Cc: Catalin Marinas > Cc: Marc Zyngier > --- > arch/arm64/include/asm/el2_setup.h | 45 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 45 insertions(+) > > diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h > index ebceaae3c749b84395c9c5eccf0caf874697ad11..1e362bb3b042d51fff15a7c2abc73842930b275a 100644 > --- a/arch/arm64/include/asm/el2_setup.h > +++ b/arch/arm64/include/asm/el2_setup.h > @@ -165,6 +165,50 @@ > .Lskip_gicv3_\@: > .endm > > +/* GICv5 system register access */ > +.macro __init_el2_gicv5 > + mrs_s x0, SYS_ID_AA64PFR2_EL1 > + ubfx x0, x0, #ID_AA64PFR2_EL1_GCIE_SHIFT, #4 > + cbz x0, .Lskip_gicv5_\@ > + > + mov x0, #(1 << ICH_HFGITR_EL2_GICRCDNMIA_SHIFT | \ > + 1 << ICH_HFGITR_EL2_GICRCDIA_SHIFT | \ > + 1 << ICH_HFGITR_EL2_GICCDDI_SHIFT | \ > + 1 << ICH_HFGITR_EL2_GICCDEOI_SHIFT | \ > + 1 << ICH_HFGITR_EL2_GICCDHM_SHIFT | \ > + 1 << ICH_HFGITR_EL2_GICCRDRCFG_SHIFT | \ > + 1 << ICH_HFGITR_EL2_GICCDPEND_SHIFT | \ > + 1 << ICH_HFGITR_EL2_GICCDAFF_SHIFT | \ > + 1 << ICH_HFGITR_EL2_GICCDPRI_SHIFT | \ > + 1 << ICH_HFGITR_EL2_GICCDDIS_SHIFT | \ > + 1 << ICH_HFGITR_EL2_GICCDEN_SHIFT) Please write this as: mov x0, #(ICH_HFGITR_EL2_GICRCDNMIA | \ ICH_HFGITR_EL2_GICRCDIA | \ ICH_HFGITR_EL2_GICCDDI | \ ICH_HFGITR_EL2_GICCDEOI | \ ICH_HFGITR_EL2_GICCDHM | \ ICH_HFGITR_EL2_GICCRDRCFG | \ ICH_HFGITR_EL2_GICCDPEND | \ ICH_HFGITR_EL2_GICCDAFF | \ ICH_HFGITR_EL2_GICCDPRI | \ ICH_HFGITR_EL2_GICCDDIS | \ ICH_HFGITR_EL2_GICCDEN) which has the exact same effect, and is consistent with other uses in this file. Thanks, M. -- Without deviation from the norm, progress is not possible.