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Wed, 27 May 2026 07:05:47 +0000 Date: Wed, 27 May 2026 08:05:46 +0100 Message-ID: <86tsrtuyb9.wl-maz@kernel.org> From: Marc Zyngier To: =?UTF-8?B?Ill1LUNodW4gTGluIFvmnpfnpZDlkJtdIg==?= Cc: "linux-arm-kernel@lists.infradead.org" , "linux-acpi@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , "Catalin\ Marinas" , Will Deacon , "Rafael J.\ Wysocki" , Mark Rutland , "Daniel\ Lezcano" , Thomas Gleixner , "Rob\ Herring" , Krzysztof Kozlowski , "Conor\ Dooley" , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , "Neil\ Armstrong" , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Ge Gordon , "BST\ Linux Kernel Upstream Group" , Jesper Nilsson , Lars Persson , Alim Akhtar , Ivaylo Ivanov , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Dinh Nguyen , Matthias Brugger , AngeloGioacchino Del Regno , Thierry Reding , Jonathan Hunter , "Bjorn\ Andersson" , Konrad Dybcio , Andreas =?UTF-8?B?RsOkcmJlcg==?= , Heiko Stuebner , Shawn Lin , Orson Zhai , Baolin Wang , "Michal\ Simek" Subject: Re: [PATCH v3 14/17] arm64: dts: realtek: Add EL2 virtual timer interrupt In-Reply-To: <6fe3e828f8724424bc6aef818ae0aa0f@realtek.com> References: <20260523140242.586031-1-maz@kernel.org> <20260523140242.586031-15-maz@kernel.org> <6fe3e828f8724424bc6aef818ae0aa0f@realtek.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; 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SAEximRunCond expanded to false On Wed, 27 May 2026 07:36:18 +0100, "Yu-Chun Lin [=E6=9E=97=E7=A5=90=E5=90=9B]" wrote: >=20 > > Subject: [PATCH v3 14/17] arm64: dts: realtek: Add EL2 virtual timer in= terrupt > >=20 > > The ARMv8.2 based CPUs used in a number of Realtek SoCs are missing the > > EL2 virtual timer interrupt. Add it. > >=20 > > Furthermore, the "kent" platform appears to assign PPI9 to both the > > EL2 virtual timer and the GIC Maintenance Interrupt, which can't be rig= ht. > > Attempt a fix by setting the former to PPI12, as PPI9 is traditionally = wired to > > the GIC itself. > >=20 > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/boot/dts/realtek/kent.dtsi | 2 +- > > arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 3 ++- > > 2 files changed, 3 insertions(+), 2 deletions(-) > >=20 > > diff --git a/arch/arm64/boot/dts/realtek/kent.dtsi > > b/arch/arm64/boot/dts/realtek/kent.dtsi > > index ae006ce244205..4147e4269247a 100644 > > --- a/arch/arm64/boot/dts/realtek/kent.dtsi > > +++ b/arch/arm64/boot/dts/realtek/kent.dtsi > > @@ -23,7 +23,7 @@ timer { > > , > > , > > , > > - ; > > + ; >=20 > Thanks for this patch. However, the 5th interrupt should be >=20 > ; I suspected as much, but it was hard to know exactly how wrong the original descriptor was, so I decided to change as little as possible. It has no material impact on the interrupt, as the GIC has no way to distinguish LEVEL_HIGH from LEVEL_LOW (it only distinguishes between LEVEL and EDGE). So this only serves as documentation. >=20 > If you are ok with it, I will amend it when applying. Please go ahead. Thanks, M. --=20 Without deviation from the norm, progress is not possible.