From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B83F41EB5E3; Thu, 1 May 2025 14:15:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746108949; cv=none; b=CsYx7tA8jH3gx1ZTWXxCix/xR8AJk2JBLbpXWim1wV89d+s8uLzOwiAWpE+qyI+VmAFX2GgXp2Oi8hp4Ad8EQO9UTKqtMiJJjYuAxbqh1G/LieomVEM1b1Pny4LwcWJdE15WvIBsvICONRlXMBwYmO7+SekPrh6AwdvwdiD6QoU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746108949; c=relaxed/simple; bh=1nOlq6ghOjjU/aPiN73OkFKaq0mCidAfYeEyCm9Uf/c=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=KY93pZ+XmsPe/2J8n7oKhIaCp71dyiiQU3X1NR7JxQKHTDcSQZ4JVnxBIzVTv4WB0pPyJhXlhacxwy7YCzVAzD1oI5uba7SVG2JOc4fVeW/W1bcQvaYnWmsCZPZH4aejguyZaBhSPNmbusazq/GmbK4v9db+8qWpgZp2UQf+fmM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=emkfsgyP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="emkfsgyP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 79654C4CEE3; Thu, 1 May 2025 14:15:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746108949; bh=1nOlq6ghOjjU/aPiN73OkFKaq0mCidAfYeEyCm9Uf/c=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=emkfsgyPoPoSWyMrc0hiZTuc1So10KqEGBTHeq7xiB7WyCR52Bjb99nHdHYFmr58K q/QOAVGPtSQ0ZdfKUsA/G0ZZXLo6E6TKWJzMfiC1WZcbfrCEDUmDq8h+aZEo8rU6/E fwNg0gXMatPTNKRTJrRWt6sWpfA4FTmDh5A0z/xTko3LvP8BjlLOT74HfMc88zOotk xZB5uIAejM0lzroKQdngOAcmH1XthTo4rdO9NfK9qZ2nYIDu6kxsTlSe5srk32MKVD +VIVfUJbS8KHjNpTVW7ZXI9hOdtb1y3IDNGGR8qf1IH2tpB2LuTAe6LESxiHv25nbV yW1cFqW67wW9Q== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uAUhX-00Ab1W-IH; Thu, 01 May 2025 15:15:47 +0100 Date: Thu, 01 May 2025 15:15:46 +0100 Message-ID: <86tt64h0x9.wl-maz@kernel.org> From: Marc Zyngier To: Lorenzo Pieralisi Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 21/22] irqchip/gic-v5: Add GICv5 IWB support In-Reply-To: References: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> <20250424-gicv5-host-v2-21-545edcaf012b@kernel.org> <867c31j20i.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: lpieralisi@kernel.org, tglx@linutronix.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, sascha.bischoff@arm.com, timothy.hayes@arm.com, Liam.Howlett@oracle.com, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Wed, 30 Apr 2025 17:25:24 +0100, Lorenzo Pieralisi wrote: > > I wrote a diff against the heavily reworked series in progress I have, > (so it does not apply on v2 - headers moved) with what I came up with > for the IWB MBIgen like. It works - it removes lots of boilerplate code > but there is a hack we never really liked in: > > gicv5_its_msi_prepare() > > that is, using the OF compatible string to detect if we are an IWB or not. You shouldn't need that. The MSI_FLAG_USE_DEV_FWNODE should be a good enough indication that this is something of interest, and that ends-up in the .init_dev_msi_info() callback. > If we are, we use the msi_alloc_info_t->hwirq to define the LPI eventid, > basically the IWB wire, if not we just allocate an eventid available from > the device bitmap. > > Other than that (and being forced to provide an IWB irqchip.irq_write_msi_msg() > pointer even if the IWB can't write anything otherwise we dereference > NULL) this works. Not even MBIGEN allows you to change the event. If you really want to ensure things are even tighter, invent a MSI_FLAG_HARDCODED_MSG flag, and pass that down the prepare path. > Is there a better way to implement this ? I would post this code with > v3 but instead of waiting I thought I could inline it here, feel free > to ignore it (or flame me if it is a solved problem I failed to spot, > we need to find a way for the IWB driver to pass the "fixed event" info > to the ITS - IWB eventIDs are hardwired it is not like the MBIgen where > the irq_write_msi_msg() callback programs the wire-to-eventid > translation in HW). It's *exactly* the same. And see above for a potential explicit solution. The empty irq_write_msi_msg() is not a problem. It's actually pretty clean, given how the whole thing works. Please fold this into your v3, and we'll take it from there. M. -- Without deviation from the norm, progress is not possible.