From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 165C41B81D3; Wed, 4 Mar 2026 14:32:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772634770; cv=none; b=JxE03RM8NC8seSoBttddqZ3uQcNKRU8XswmXBQFKwOkM2Q9lzspC2HH0OzKHOxVbRyQMefMvetCZLDQJjpe6OB2H2Ii8GlfwSCcdMBTc3mpldFKV3u0eRyKIwLaJnHVxUcDjHOzYu7YNMWF/yBWBiWIi0Sfzr9qFcXdiLokpMxY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772634770; c=relaxed/simple; bh=YDfupv+OiYKnp7AvB0Ml43DchZjjAoXwu1UUQHBrbaY=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=NBa+EHrWXx4EjiKoO8fzMNknj+2G/s8vntyjGZGU3nZrKc5alndZLsMqAEXoy4+gHwdQSEdn8QAf/u/Cnfwkd7G6TN78rDbTAifTgeJQyPMMWBOwOU2P6vwG/jUncjtswj4ag9GnjuSWWfhVGHlOXd2AS94+5AdOG1ltjDEKFn8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HGsssrn9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HGsssrn9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AAA19C2BC87; Wed, 4 Mar 2026 14:32:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772634769; bh=YDfupv+OiYKnp7AvB0Ml43DchZjjAoXwu1UUQHBrbaY=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=HGsssrn9Gq1+4Fc4oTodJSyY6ucW0H4hxWeIup79s/MYkX5MWMdxmusSpHSEaJ9DP WZ5RsVtpqYUnliGiuE+0OXLIxCOHKK/Kn/sDkeoQxsluDxtH6QhDykAfPQjW+3PnO6 G8S3FDcuVvBK/IFWo8yd+chJuOnE8AW8bEKyyeRqCzYi/FRXBl8oaC+dKh8IlUnfgc kzMCaBMgnUZNS/4dgFqWmGIgVWtSeE6hEnTwLsE2046o8+1JuII+DWINugUNLJatxy WZOzGpKsrESX4xcaTjigohCSLeinUVL/Vmt7912kiexjUVQfn6/EfS0wU/uVVnLzl/ PEgky7kzM5eqg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vxnHL-0000000G4kR-2G37; Wed, 04 Mar 2026 14:32:47 +0000 Date: Wed, 04 Mar 2026 14:32:47 +0000 Message-ID: <86y0k77jhs.wl-maz@kernel.org> From: Marc Zyngier To: Geert Uytterhoeven Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] dt-bindings: interrupt-controller: arm,gic-v3: Fix EPPI range In-Reply-To: <107183629106ad392e17fdf539a3d79873024377.1772632987.git.geert+renesas@glider.be> References: <107183629106ad392e17fdf539a3d79873024377.1772632987.git.geert+renesas@glider.be> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: geert+renesas@glider.be, tglx@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Wed, 04 Mar 2026 14:04:10 +0000, Geert Uytterhoeven wrote: > > According to the "Arm Generic Interrupt Controller (GIC) Architecture > Specification, v3 and v3", revision H.b[1], there can be only 64 v3 and v4? > Extended PPI interrupts. > > [1] https://developer.arm.com/documentation/ihi0069/hb/ > > Fixes: 4b049063e0bcbfd3 ("dt-bindings: interrupt-controller: arm,gic-v3: Describe EPPI range support") > Signed-off-by: Geert Uytterhoeven > --- > .../devicetree/bindings/interrupt-controller/arm,gic-v3.yaml | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml > index bfd30aae682bf3f7..360a0643a0b567a4 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml > @@ -50,7 +50,7 @@ properties: > The 2nd cell contains the interrupt number for the interrupt type. > SPI interrupts are in the range [0-987]. PPI interrupts are in the > range [0-15]. Extended SPI interrupts are in the range [0-1023]. > - Extended PPI interrupts are in the range [0-127]. > + Extended PPI interrupts are in the range [0-63]. > > The 3rd cell is the flags, encoded as follows: > bits[3:0] trigger type and level flags. Duh. Thankfully the code didn't have the same problem... Thanks for noticing it. With the above fixed: Brain-farted-by: Marc Zyngier Acked-by: Marc Zyngier M. -- Without deviation from the norm, progress is not possible.