From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D22962586EB; Mon, 12 May 2025 08:27:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747038477; cv=none; b=a9fXrd5aLLAZLEqa9kTG/fGJvlhFUWwoqpnO/ircLzqJouClyqyQz/QsUFrBURDrSxY4Um6EmXgeoVDecxvvbYJGAGMGRKwQYGTlgdy7B8ERhw3CplIvklaxN5kysts80kckr7z9Nm4RGIVJBMH914f0w84uYxkwYSzdjrJbiX8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747038477; c=relaxed/simple; bh=foL6Xem9CuBv60/odwYwPM/LICxRkGWLh1HoI9B+9hQ=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=c8WH+QHTMc2RzRYncDk+Qbfn6Y827cLm/k/fZCpIWgbVliqpA/bs2zaDPksyN/6orV3QL/AkLJO/NXBeDN/YpnVFlnx6ZbzGx9FK5sVv5sDHVTGWuLEYNG69GK012MHrsplCTOuZ1GKtThd4xFM9PKA9xGEH1ZyTE/rotG2zCzY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=COXvj/n/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="COXvj/n/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 32C4EC4CEE7; Mon, 12 May 2025 08:27:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747038477; bh=foL6Xem9CuBv60/odwYwPM/LICxRkGWLh1HoI9B+9hQ=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=COXvj/n/lGafd9If+jgBkNCvHKMU0efW8jaBs4dmWfGerY8XVfFKuSvPR/+XItlmd p2EzelamKg7qq/76j6pRBD3toEZ0vX9ZuNW2J/npfSYyLwA6kwKMFcvTPOBozSYWIJ XqdeOC5DkITmfs12+mzxaiY16usfA9MJwfYNk2qhgueOJRWAS0ebqOqkpdsJuYUk/4 U5m2JyztXdJa8omEIr7u/r6vIyu4G6a6NlDIvzktMlt1uIJTt0AUoXwqvZbkYfVSwh DlYKKgkUlb4AiKBmSLSP30dXedisMgNJsH2EJLDlczkkmkVFTxjaK/U8nSEJhW+JkK ghVsz9GcxxNoA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uEOVu-00E2gE-OX; Mon, 12 May 2025 09:27:54 +0100 Date: Mon, 12 May 2025 09:27:54 +0100 Message-ID: <86y0v2fd2t.wl-maz@kernel.org> From: Marc Zyngier To: Lorenzo Pieralisi Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , Jiri Slaby , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v3 20/25] irqchip/gic-v5: Add GICv5 PPI support In-Reply-To: References: <20250506-gicv5-host-v3-0-6edd5a92fd09@kernel.org> <20250506-gicv5-host-v3-20-6edd5a92fd09@kernel.org> <87zffpn5rk.ffs@tglx> <86a57ohjey.wl-maz@kernel.org> <87ecx0mt9p.ffs@tglx> <867c2sh6jx.wl-maz@kernel.org> <874ixwmpto.ffs@tglx> <864ixvh4ss.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: lpieralisi@kernel.org, tglx@linutronix.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, sascha.bischoff@arm.com, timothy.hayes@arm.com, Liam.Howlett@oracle.com, mark.rutland@arm.com, jirislaby@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 08 May 2025 11:44:45 +0100, Lorenzo Pieralisi wrote: > > On Thu, May 08, 2025 at 09:42:27AM +0100, Marc Zyngier wrote: > > On Thu, 08 May 2025 08:42:41 +0100, > > Lorenzo Pieralisi wrote: > > > > > > On Wed, May 07, 2025 at 04:57:07PM +0200, Thomas Gleixner wrote: > > > > On Wed, May 07 2025 at 14:52, Marc Zyngier wrote: > > > > > On Wed, 07 May 2025 14:42:42 +0100, > > > > > Thomas Gleixner wrote: > > > > >> > > > > >> On Wed, May 07 2025 at 10:14, Marc Zyngier wrote: > > > > >> > On Tue, 06 May 2025 16:00:31 +0100, > > > > >> > Thomas Gleixner wrote: > > > > >> >> > > > > >> >> How does this test distinguish between LEVEL_LOW and LEVEL_HIGH? It only > > > > >> >> tests for level, no? So the test is interesting at best ... > > > > >> > > > > > >> > There is no distinction between HIGH and LOW, RISING and FALLING, in > > > > >> > any revision of the GIC architecture. > > > > >> > > > > >> Then pretending that there is a set_type() functionality is pretty daft > > > > > > > > > > You still need to distinguish between level and edge when this is > > > > > programmable (which is the case for a subset of the PPIs). > > > > > > > > Fair enough, but can we please add a comment to this function which > > > > explains this oddity. > > > > > > Getting back to this, I would need your/Marc's input on this. > > > > > > I think it is fair to remove the irq_set_type() irqchip callback for > > > GICv5 PPIs because there is nothing to set, as I said handling mode > > > for these IRQs is fixed. I don't think this can cause any trouble > > > (IIUC a value within the IRQF_TRIGGER_MASK should be set on requesting > > > an IRQ to "force" the trigger to be programmed and even then core code > > > would not fail if the irq_set_type() irqchip callback is not > > > implemented). > > > > > > I am thinking about *existing* drivers that request GICv3 PPIs with > > > values in IRQF_TRIGGER_MASK set (are there any ? Don't think so but you > > > know better than I do), when we switch over to GICv5 we would have no > > > irq_set_type() callback for PPIs but I think we are still fine, not > > > implementing irqchip.irq_set_type() is correct IMO. > > > > Nobody seems to use a hardcoded trigger (well, there is one exception, > > but that's to paper over a firmware bug). > > That's what I get if I remove the PPI irq_set_type() callback (just one > timer, removed others because they add nothing) and enable debug for > kernel/irq/manage.c (+additional printout): > > genirq: No set_type function for IRQ 70 (GICv5-PPI) > __irq_set_trigger+0x13c/0x180 > __setup_irq+0x3d8/0x7c0 > __request_percpu_irq+0xbc/0x114 > arch_timer_register+0x84/0x140 > arch_timer_of_init+0x180/0x1d0 > timer_probe+0x74/0x124 > time_init+0x18/0x58 > start_kernel+0x198/0x384 > __primary_switched+0x88/0x90 > > arch_timer: check_ppi_trigger irq 70 flags 8 > genirq: enable_percpu_irq irq 70 type 8 > genirq: No set_type function for IRQ 70 (GICv5-PPI) > __irq_set_trigger+0x13c/0x180 > enable_percpu_irq+0x100/0x140 > arch_timer_starting_cpu+0x54/0xb8 > cpuhp_issue_call+0x254/0x3a8 > __cpuhp_setup_state_cpuslocked+0x208/0x2c8 > __cpuhp_setup_state+0x50/0x74 > arch_timer_register+0xc4/0x140 > arch_timer_of_init+0x180/0x1d0 > timer_probe+0x74/0x124 > time_init+0x18/0x58 > start_kernel+0x198/0x384 > __primary_switched+0x88/0x90 > > I noticed that, if the irq_set_type() function is not implemented, > we don't execute (in __irq_set_trigger()): > > irq_settings_set_level(desc); > irqd_set(&desc->irq_data, IRQD_LEVEL); > > which in turn means that irqd_is_level_type(&desc->irq_data) is false > for PPIs (ie arch timers, despite being level interrupts). > > An immediate side effect is that they show as edge in: > > /proc/interrupts > > but that's just what I could notice. > > Should I set them myself in PPI translate/alloc functions ? When I say "do it in alloc", I mean "do whatever is needed to set things up so that we can safely ignore the absence of the .irq_set_type() callback -- this may even include some slight modification of the core code, but that's not big deal". > Removing the irq_set_type() for PPIs does not seem so innocuous, it is a > bit complex to check all ramifications, please let me know if you spot > something I have missed. See above. > > > > On the other hand, given that on GICv5 PPI handling mode is fixed, > > > do you think that in the ppi_irq_domain_ops.translate() callback, > > > I should check the type the firmware provided and fail the translation > > > if it does not match the HW hardcoded value ? > > > > Why? The fact that the firmware is wrong doesn't change the hardware > > integration. It just indicates that whoever wrote the firmware didn't > > read the documentation. > > > > Even more, I wonder what the benefit of having that information in the > > firmware tables if the only thing that matters in the immutable HW > > view. Yes, having it in the DT/ACPI simplifies the job of the kernel > > (only one format to parse). But it is overall useless information. > > Yes, that I agree but it would force firmware bindings to special case > PPIs to remove the type (#interrupt-cells and co.). > > From what I read I understand I must ignore the PPI type provided by > firmware. You could warn on spotting that is inconsistent, but the HW view is the only one that actually matters. M. -- Without deviation from the norm, progress is not possible.