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Wed, 10 Jul 2024 10:01:39 +0100 Date: Wed, 10 Jul 2024 10:01:22 +0100 Message-ID: <86y16939jx.wl-maz@kernel.org> From: Marc Zyngier To: Cc: , , , , , , , , , , , Subject: Re: [PATCH v5 15/27] dt-bindings: interrupt-controller: Document the property microchip,nr-irqs In-Reply-To: <82ca4f3d-fa78-4617-823e-69f16a2c3319@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> <20240703102814.196063-1-varshini.rajendran@microchip.com> <20240703-dentist-wired-bdb063522ef7@spud> <82ca4f3d-fa78-4617-823e-69f16a2c3319@microchip.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.3 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: Nicolas.Ferre@microchip.com, Varshini.Rajendran@microchip.com, conor@kernel.org, tglx@linutronix.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, claudiu.beznea@tuxon.dev, Dharma.B@microchip.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 09 Jul 2024 15:06:29 +0100, wrote: > > On 09/07/2024 at 08:13, Varshini Rajendran - I67070 wrote: > > On 03/07/24 9:11 pm, Conor Dooley wrote: > >> On Wed, Jul 03, 2024 at 03:58:14PM +0530, Varshini Rajendran wrote: > >>> Add the description and conditions to the device tree documentation > >>> for the property microchip,nr-irqs. > >>> > >>> Signed-off-by: Varshini Rajendran > >> This needs to be part of patch 14. > >> > >>> --- > >>> .../bindings/interrupt-controller/atmel,aic.yaml | 12 ++++++++++++ > >>> 1 file changed, 12 insertions(+) > >>> > >>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml > >>> index 9c5af9dbcb6e..06e5f92e7d53 100644 > >>> --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml > >>> +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml > >>> @@ -54,6 +54,10 @@ properties: > >>> $ref: /schemas/types.yaml#/definitions/uint32-array > >>> description: u32 array of external irqs. > >>> > >>> + microchip,nr-irqs: > >>> + $ref: /schemas/types.yaml#/definitions/uint32-array > >>> + description: u32 array of nr_irqs. > >> This makes no sense, did you just copy from above? Why would the number > >> of irqs be an array? Why can't you determine this from the compatble? > >> > > Sorry for the bad description. I will correct it in the next version. > > > > For the second part of the question, this change was done as a step to > > resolve having a new compatible while having practically the same IP > > pointed out in the v3 of the series [1]. It is kind of looping back to > > the initial idea now. Even if this is added as a driver data, it > > overrides the expectation from the comment in [1]. Please suggest. I > > In your v3 patch, indeed you were extracting the number of IRQs from the > compatibility string (aka, from device tree...). It's my preferred > solution as well. > > So, come back to v3 [1] and address what Conor said in v4 "...having > specific $soc_aic5_of_init() functions for each SoC seems silly when > usually only the number of interrupts changes. The number of IRQs could > be in the match data and you could use aic5_of_init in your > IRQCHIP_DECLARE directly" > > I think that we can convince Marc/Thomas that it's the best option as it > prevents introducing another non-standard property to the DT, break the > ABI (and was used happily for years). In general, the least cruft we add to the DT after the facts, the better. If the compatible string is good enough to identify the device, I don't think we need to overthink it, specially as there is no upside to non-standard properties here -- from what I understand, the number of available interrupts is a property of the HW, and not something that can be configured, making it part of the programming model, just like the layout of registers. But I'm not in a deciding position anymore, and this is only my (educated) opinion. Thanks, M. -- Without deviation from the norm, progress is not possible.