From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66070C77B7C for ; Thu, 11 May 2023 18:43:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238741AbjEKSnE (ORCPT ); Thu, 11 May 2023 14:43:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55006 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238407AbjEKSnD (ORCPT ); Thu, 11 May 2023 14:43:03 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 43E2AE54 for ; Thu, 11 May 2023 11:43:02 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 7335F60686 for ; Thu, 11 May 2023 18:43:01 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C1FB7C433D2; Thu, 11 May 2023 18:43:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683830580; bh=Fz7ns3dw4s4B8m22yD4acU8UM/HfzTj11w01+er2SLo=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=Mz9WWIXOMwVt8/OS9NBts8hX2egDqXPWG8WxthDaoFdOgnDLMsOwtoGRk2PO7Zcn9 1SC3QJHI0aqx6hZiKTY+JHYS6gBrS2KSI/OC4XegyRl/TkqpiT0tIf8EmrJevuhDd6 Z4ftxrWtnr/Y3ieYg9A8tRQ00Be2n/aQmRi2IQCmkwv7LNe0+eXk390iEPG2qqxq5A mzGdvxyCNlU9vmWhDBL3gchFNNi89lRwm1OoDjhszqRPsJh5x6mCYLaKvwVDivMdc2 I4mNybGs8vxMgPFRK2eGMWylX+zZ9In2YKQbBc4p6j5FErkLyB4x0Q3rt0OfXFqrQG iq1Hdx0DEsGhg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1pxBFi-00EPsf-Gr; Thu, 11 May 2023 19:42:58 +0100 Date: Thu, 11 May 2023 19:42:58 +0100 Message-ID: <86y1lun1zh.wl-maz@kernel.org> From: Marc Zyngier To: Catalin Marinas Cc: James Morse , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Will Deacon , Mark Rutland , Lorenzo Pieralisi , Sudeep Holla , Oliver Upton , Rob Herring , Krzysztof Kozlowski Subject: Re: [PATCH 0/6] arm64: errata: Disable FWB on parts with non-ARM interconnects In-Reply-To: References: <20230330165128.3237939-1-james.morse@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: catalin.marinas@arm.com, james.morse@arm.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, will@kernel.org, mark.rutland@arm.com, lpieralisi@kernel.org, sudeep.holla@arm.com, oliver.upton@linux.dev, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, 11 May 2023 18:15:15 +0100, Catalin Marinas wrote: > > Hi James, > > On Thu, Mar 30, 2023 at 05:51:22PM +0100, James Morse wrote: > > When stage1 translation is disabled, the SCTRL_E1.I bit controls the > > attributes used for instruction fetch, one of the options results in a > > non-cacheable access. A whole host of CPUs missed the FWB override > > in this case, meaning a KVM guest could fetch stale/junk data instead of > > instructions. > > > > The workaround is to disable FWB, and do the required cache maintenance > > instead. > > I think the workaround can be to only do the required cache maintenance > without disabling FWB. Having FWB on doesn't bring any performance > benefits if we do the cache maintenance anyway but keeping it around may > be useful for other reasons (e.g. KVM device pass-through using > cacheable mappings, though not something KVM supports currently). But you'd also rely on the guest doing its own cache maintenance for instructions it writes, right? Which probably means exposing a different CLIDR_EL1 so that LoC/LoUU/LoUIS are consistent with *not* having FWB... I also wonder if keeping FWB set has the potential to change the semantics of the CMOs (the spec seems silent on that front). > > Unfortunately, no-one has firmware that supports this new interface yet, > > and the least surprising thing to do is to enable the workaround by default, > > meaning FWB is disabled on all these cores, even for unaffected platforms. > > ACPI Platforms that are not-affected can either take a firmware-update to > > support the interface, or if the kernel they run will only run on hardware > > that is unaffected, disable the workaround at build time. > > Given that we know of more platforms that are _not_ affected and vendors > are pretty vague on whether they need this, I'd rather swap the default > and keep the workaround off with a firmware interface, DT or command > line opt-in. That'd be my preferred way. I really dislike putting the onus on working systems to declare themselves safe (although there are some Spectre-shaped precedents to that). > That said, maybe we can reduce the risk further by doing the > vcpu_has_run_once() trick with !FWB and clean the D side to PoC on a > stage 2 exec fault (together with the I-cache invalidation). We can then > ignore any other cache maintenance on S2 faults until someone shouts (we > can maybe recommend forcing FWB off on the command line through the > cpuid override). You lost me here with your vcpu_has_run_once(). Keeping the CMOs on exec fault is definitely manageable. But is that enough? Thanks, M. -- Without deviation from the norm, progress is not possible.