* [RFC PATCH] ARM: dts: renesas: r9a06g032-rzn1d400-db: add QSPI node including NOR flash
@ 2026-01-16 11:48 Wolfram Sang
2026-01-16 16:08 ` Miquel Raynal
2026-01-19 16:40 ` Geert Uytterhoeven
0 siblings, 2 replies; 4+ messages in thread
From: Wolfram Sang @ 2026-01-16 11:48 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Miquel Raynal, Wolfram Sang, Geert Uytterhoeven, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree
Enable the QSPI controller to access the connected SPI NOR flash. The
NOR datasheet may suggest faster tuning parameters but those did not
work on my board.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
Depends on the series "[PATCH v2 00/13] spi: cadence-qspi: Add Renesas
RZ/N1 support". As this is still under discussion, this patch is RFC
only.
The tuning values used came from Miquel and work here as well. An
interested party may try to tune this further but I will go the safe
route here.
The partitioning comes from the BSP. Using these partitions, I actually
discovered previous kernels and DTBs from the previous owner of the
board :)
Thanks and happy hacking, everyone!
.../dts/renesas/r9a06g032-rzn1d400-db.dts | 78 +++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
index 4a72aa7663f2..0e23aa8aa55b 100644
--- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
+++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
@@ -300,6 +300,84 @@ pins_mdio1: pins_mdio1 {
pinmux = <RZN1_PINMUX(152, RZN1_FUNC_MDIO1_SWITCH)>,
<RZN1_PINMUX(153, RZN1_FUNC_MDIO1_SWITCH)>;
};
+
+ pins_qspi0: pins_qspi0 {
+ pinmux = <RZN1_PINMUX(74, RZN1_FUNC_QSPI)>,
+ <RZN1_PINMUX(75, RZN1_FUNC_QSPI)>,
+ <RZN1_PINMUX(76, RZN1_FUNC_QSPI)>,
+ <RZN1_PINMUX(77, RZN1_FUNC_QSPI)>,
+ <RZN1_PINMUX(78, RZN1_FUNC_QSPI)>,
+ <RZN1_PINMUX(79, RZN1_FUNC_QSPI)>;
+ bias-disable;
+ };
+};
+
+&qspi0 {
+ pinctrl-0 = <&pins_qspi0>;
+ pinctrl-names = "default";
+ status = "okay";
+ bootph-all;
+
+ flash@0 {
+ reg = <0>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <62500000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ cdns,read-delay = <1>;
+ cdns,tshsl-ns = <200>;
+ cdns,tsd2d-ns = <255>;
+ cdns,tchsh-ns = <20>;
+ cdns,tslch-ns = <20>;
+ bootph-all;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ /* 64KB */
+ label = "qspi0:spl";
+ reg = <0x0000000 0x00010000>;
+ };
+ partition@1 {
+ /* 64KB */
+ label = "qspi0:pkgt";
+ reg = <0x0010000 0x00010000>;
+ };
+ partition@2 {
+ /* 512KB */
+ label = "qspi0:u-boot";
+ reg = <0x0020000 0x00080000>;
+ };
+ partition@3 {
+ /* 64KB */
+ label = "qspi0:env";
+ reg = <0x00a0000 0x00010000>;
+ };
+ partition@4 {
+ /* 128KB */
+ label = "qspi0:dtb";
+ reg = <0x00b0000 0x00020000>;
+ };
+ partition@5 {
+ /* 1MB */
+ label = "qspi0:cm3";
+ reg = <0x00d0000 0x00100000>;
+ };
+ partition@6 {
+ /* 6MB */
+ label = "qspi0:kernel";
+ reg = <0x01d0000 0x00600000>;
+ };
+ partition@7 {
+ /* Remaining */
+ label = "qspi0:data";
+ reg = <0x07d0000 0>;
+ };
+ };
+ };
};
&rtc0 {
--
2.47.3
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [RFC PATCH] ARM: dts: renesas: r9a06g032-rzn1d400-db: add QSPI node including NOR flash
2026-01-16 11:48 [RFC PATCH] ARM: dts: renesas: r9a06g032-rzn1d400-db: add QSPI node including NOR flash Wolfram Sang
@ 2026-01-16 16:08 ` Miquel Raynal
2026-01-18 8:58 ` Wolfram Sang
2026-01-19 16:40 ` Geert Uytterhoeven
1 sibling, 1 reply; 4+ messages in thread
From: Miquel Raynal @ 2026-01-16 16:08 UTC (permalink / raw)
To: Wolfram Sang
Cc: linux-renesas-soc, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree
Hello Wolfram,
On 16/01/2026 at 12:48:48 +01, Wolfram Sang <wsa+renesas@sang-engineering.com> wrote:
> Enable the QSPI controller to access the connected SPI NOR flash. The
> NOR datasheet may suggest faster tuning parameters but those did not
> work on my board.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> ---
>
> Depends on the series "[PATCH v2 00/13] spi: cadence-qspi: Add Renesas
> RZ/N1 support". As this is still under discussion, this patch is RFC
> only.
>
> The tuning values used came from Miquel and work here as well. An
> interested party may try to tune this further but I will go the safe
> route here.
In case you feel adventurous, this paragraph made me remember that I had
noted down some slightly more aggressive values related to the DB board
(which I don't have) in some of my notes. A bit of digging resurrected
the following:
tshsl-ns = <30>;
tsd2d-ns = <3>;
tchsh-ns = <3>;
tslch-ns = <3>;
Anyhow, thanks for the follow-up patch and thanks for testing.
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Thanks,
Miquèl
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [RFC PATCH] ARM: dts: renesas: r9a06g032-rzn1d400-db: add QSPI node including NOR flash
2026-01-16 16:08 ` Miquel Raynal
@ 2026-01-18 8:58 ` Wolfram Sang
0 siblings, 0 replies; 4+ messages in thread
From: Wolfram Sang @ 2026-01-18 8:58 UTC (permalink / raw)
To: Miquel Raynal
Cc: linux-renesas-soc, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree
[-- Attachment #1: Type: text/plain, Size: 704 bytes --]
> > The tuning values used came from Miquel and work here as well. An
> > interested party may try to tune this further but I will go the safe
> > route here.
>
> In case you feel adventurous, this paragraph made me remember that I had
> noted down some slightly more aggressive values related to the DB board
> (which I don't have) in some of my notes. A bit of digging resurrected
> the following:
>
> tshsl-ns = <30>;
> tsd2d-ns = <3>;
> tchsh-ns = <3>;
> tslch-ns = <3>;
Yes, these values can be found in the BSP and could be deduced from the
SPI-NOR datasheet, too. However, I got -ETIMEDOUT with these. Didn't
investigate further (and no time to do so).
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [RFC PATCH] ARM: dts: renesas: r9a06g032-rzn1d400-db: add QSPI node including NOR flash
2026-01-16 11:48 [RFC PATCH] ARM: dts: renesas: r9a06g032-rzn1d400-db: add QSPI node including NOR flash Wolfram Sang
2026-01-16 16:08 ` Miquel Raynal
@ 2026-01-19 16:40 ` Geert Uytterhoeven
1 sibling, 0 replies; 4+ messages in thread
From: Geert Uytterhoeven @ 2026-01-19 16:40 UTC (permalink / raw)
To: Wolfram Sang
Cc: linux-renesas-soc, Miquel Raynal, Geert Uytterhoeven, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree
Hi Wolfram,
On Fri, 16 Jan 2026 at 12:49, Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> Enable the QSPI controller to access the connected SPI NOR flash. The
> NOR datasheet may suggest faster tuning parameters but those did not
> work on my board.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Thanks for your patch!
> --- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
> +++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
> @@ -300,6 +300,84 @@ pins_mdio1: pins_mdio1 {
> pinmux = <RZN1_PINMUX(152, RZN1_FUNC_MDIO1_SWITCH)>,
> <RZN1_PINMUX(153, RZN1_FUNC_MDIO1_SWITCH)>;
> };
> +
> + pins_qspi0: pins_qspi0 {
> + pinmux = <RZN1_PINMUX(74, RZN1_FUNC_QSPI)>,
> + <RZN1_PINMUX(75, RZN1_FUNC_QSPI)>,
> + <RZN1_PINMUX(76, RZN1_FUNC_QSPI)>,
> + <RZN1_PINMUX(77, RZN1_FUNC_QSPI)>,
> + <RZN1_PINMUX(78, RZN1_FUNC_QSPI)>,
> + <RZN1_PINMUX(79, RZN1_FUNC_QSPI)>;
> + bias-disable;
> + };
> +};
> +
> +&qspi0 {
> + pinctrl-0 = <&pins_qspi0>;
> + pinctrl-names = "default";
> + status = "okay";
> + bootph-all;
> +
> + flash@0 {
> + reg = <0>;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <62500000>;
> + spi-rx-bus-width = <4>;
> + spi-tx-bus-width = <4>;
> + cdns,read-delay = <1>;
> + cdns,tshsl-ns = <200>;
> + cdns,tsd2d-ns = <255>;
> + cdns,tchsh-ns = <20>;
> + cdns,tslch-ns = <20>;
> + bootph-all;
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition@0 {
> + /* 64KB */
KiB (everywhere)
> + label = "qspi0:spl";
Is there any point in the "qspi0:"-prefixes?
AFAIU, RZ/N1D supports only a single QSPI instance.
> + reg = <0x0000000 0x00010000>;
> + };
> + partition@1 {
partition@10000 (reg address, everywhere)
> + /* 64KB */
> + label = "qspi0:pkgt";
> + reg = <0x0010000 0x00010000>;
> + };
> + partition@2 {
> + /* 512KB */
> + label = "qspi0:u-boot";
> + reg = <0x0020000 0x00080000>;
> + };
> + partition@3 {
> + /* 64KB */
> + label = "qspi0:env";
> + reg = <0x00a0000 0x00010000>;
> + };
> + partition@4 {
> + /* 128KB */
> + label = "qspi0:dtb";
> + reg = <0x00b0000 0x00020000>;
> + };
> + partition@5 {
> + /* 1MB */
MiB (everywhere)
> + label = "qspi0:cm3";
> + reg = <0x00d0000 0x00100000>;
> + };
> + partition@6 {
> + /* 6MB */
> + label = "qspi0:kernel";
> + reg = <0x01d0000 0x00600000>;
> + };
> + partition@7 {
> + /* Remaining */
> + label = "qspi0:data";
> + reg = <0x07d0000 0>;
reg size should be 0x1830000.
> + };
> + };
> + };
> };
The rest LGTM.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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2026-01-16 11:48 [RFC PATCH] ARM: dts: renesas: r9a06g032-rzn1d400-db: add QSPI node including NOR flash Wolfram Sang
2026-01-16 16:08 ` Miquel Raynal
2026-01-18 8:58 ` Wolfram Sang
2026-01-19 16:40 ` Geert Uytterhoeven
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