From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2FE01547C3; Thu, 3 Apr 2025 17:27:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743701276; cv=none; b=TPmt2fbroyjRvejK/e4nkzCzGhF8O9zSavEZX3kdVY1CjucNLAXRZwVQSvdQi5iGcUQHPSjoJNQH+M2MihgRt9zIEC02B1cb/bI8i64zhhR54ZlYC5eB05lvXESOw5Ii1OFw+J/2KONdgnJZ1ODDb28cbYi7tGKA9cLDux/OEJQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743701276; c=relaxed/simple; bh=bYRGDxwUgmJOdrUaQaMSOv+cxYHSKhylhTsWPM09ziw=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=LsEsPfU2+wTLepitCHhSlOPrp5Uq6b8O3HsQYB6bsZgOvN1gZh+1jUxTzGCOOIgH6vs6xSOEzD9sefAfgtx5wlpa4ZSgWT1OXpj64fV8h8NnJswr7lgjkvFviGsbeH93tWK8wFLZBNm32o/dJ1igJ3jAU/AD9C4i+sTfIy/UFGo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uTy9IWnZ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uTy9IWnZ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 11BB5C4CEE3; Thu, 3 Apr 2025 17:27:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743701276; bh=bYRGDxwUgmJOdrUaQaMSOv+cxYHSKhylhTsWPM09ziw=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=uTy9IWnZfGwj/kOhXEx60AAN+jzV4EcbW45eoOMKQf2yLE48fMFvIx+wyTf0eyIGn rVTUe1L26I6oh1IKpyXZy1ZL2+5peL3p9EDWNTmIIR7yBo+sS56xGY/K2Ri1KTxpGD m4J+ta6FC7L6M2IE8e/vJz13uEvUN6i/E7yuxffoXJGSA1UuMPMtYNQsnonLM249q4 rAUYwI5ZCT/IL8Betqt01DBc0D8MqlJKTBcWUFX5IVRSrpc28QeTupRm9jol3oWB6i U/oRgG2O4Dmovd4zjyGpfjAcK7DhYe0ZXaRq0yxzWAldZmLUxhOPqnqwLATPlCD0IK 0sDrtAMzw1aIg== Received: from sofa.misterjones.org ([185.219.108.64] helo=lobster-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1u0OM5-0021yp-KD; Thu, 03 Apr 2025 18:27:53 +0100 Date: Thu, 03 Apr 2025 18:27:55 +0100 Message-ID: <874iz5yx2c.wl-maz@kernel.org> From: Marc Zyngier To: Christian Bruel Cc: , , , , , , , , , Subject: Re: [PATCH 3/3] arm64: dts: st: add st,stm32mp2-cortex-a7-gic in intc node in stm32mp251.dtsi In-Reply-To: <20250403122805.1574086-4-christian.bruel@foss.st.com> References: <20250403122805.1574086-1-christian.bruel@foss.st.com> <20250403122805.1574086-4-christian.bruel@foss.st.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: christian.bruel@foss.st.com, tglx@linutronix.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 03 Apr 2025 13:28:05 +0100, Christian Bruel wrote: > > Add st,stm32mp2-cortex-a7-gic to enable the GICC_DIR register remap > > Signed-off-by: Christian Bruel > --- > arch/arm64/boot/dts/st/stm32mp251.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi > index f3c6cdfd7008..030e5da67a7e 100644 > --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi > +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi > @@ -115,7 +115,7 @@ scmi_vdda18adc: regulator@7 { > }; > > intc: interrupt-controller@4ac00000 { > - compatible = "arm,cortex-a7-gic"; > + compatible = "st,stm32mp2-cortex-a7-gic", "arm,cortex-a7-gic"; What nonsense is this? This is an *arm64* machine, with I expect a GIC400. Where is this A7 compat coming from? M. -- Jazz isn't dead. It just smells funny.