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From: Marc Zyngier <maz@kernel.org>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: Daniel Palmer <daniel@0x0f.com>,
	DTML <devicetree@vger.kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	Romain Perier <romain.perier@gmail.com>
Subject: Re: [PATCH 2/3] irqchip: SigmaStar SSD20xD gpi
Date: Thu, 30 Sep 2021 14:06:01 +0100	[thread overview]
Message-ID: <874ka2tdqe.wl-maz@kernel.org> (raw)
In-Reply-To: <CACRpkdYLURJCopH3hDuZTY8ce9-OxakELyFqwqkAVCsYmzF5kg@mail.gmail.com>

[huh, missed this email...]

On Tue, 21 Sep 2021 19:23:04 +0100,
Linus Walleij <linus.walleij@linaro.org> wrote:
> 
> On Tue, Sep 21, 2021 at 10:27 AM Marc Zyngier <maz@kernel.org> wrote:
> 
> > Linus: is there a reason why the gpiolib insist on setting its own
> > handler while building the hierarchy?
> 
> Is it this?
> 
>         /*
>          * We set handle_bad_irq because the .set_type() should
>          * always be invoked and set the right type of handler.
>          */
>         irq_domain_set_info(d,
>                             irq,
>                             hwirq,
>                             gc->irq.chip,
>                             gc,
>                             girq->handler,
>                             NULL, NULL);
>         irq_set_probe(irq);
> (...)

It is its relative position wrt to irq_domain_alloc_irqs_parent() that
has the potential for annoyance. irq_domain_set_info() will trigger an
irq startup, which will explode if the parent level hasn't been
initialised correctly.

> 
> IIUC it's because sometimes, on elder systems (such as ixp4xx) some machines
> are still using boardfiles, and drivers are not obtaining IRQs dynamically
> from device tree or ACPI, instead they are set up statically at machine
> init.
>
> I assume it would otherwise be done as part of ops->translate?

No, this is the right spot if you really need to set the handler. But
it should really be after the parent allocation (see below for
something totally untested).

Ultimately, setting the flow handler when there is a parent domain is
a bit odd, as you'd expect the root domain to be in charge of the
overall flow.

Thanks,

	M.

diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index abfbf546d159..53221d54c4be 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -1103,19 +1103,6 @@ static int gpiochip_hierarchy_irq_domain_alloc(struct irq_domain *d,
 	}
 	chip_dbg(gc, "found parent hwirq %u\n", parent_hwirq);
 
-	/*
-	 * We set handle_bad_irq because the .set_type() should
-	 * always be invoked and set the right type of handler.
-	 */
-	irq_domain_set_info(d,
-			    irq,
-			    hwirq,
-			    gc->irq.chip,
-			    gc,
-			    girq->handler,
-			    NULL, NULL);
-	irq_set_probe(irq);
-
 	/* This parent only handles asserted level IRQs */
 	parent_arg = girq->populate_parent_alloc_arg(gc, parent_hwirq, parent_type);
 	if (!parent_arg)
@@ -1137,6 +1124,18 @@ static int gpiochip_hierarchy_irq_domain_alloc(struct irq_domain *d,
 			 parent_hwirq, hwirq);
 
 	kfree(parent_arg);
+
+	if (!ret) {
+		irq_domain_set_info(d,
+				    irq,
+				    hwirq,
+				    gc->irq.chip,
+				    gc,
+				    girq->handler,
+				    NULL, NULL);
+		irq_set_probe(irq);
+	}
+
 	return ret;
 }
 

-- 
Without deviation from the norm, progress is not possible.

  parent reply	other threads:[~2021-09-30 13:06 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-14 10:04 [PATCH 0/3] SigmaStar SSD20XD GPIO interrupt controller Daniel Palmer
2021-09-14 10:04 ` [PATCH 1/3] dt-bindings: interrupt-controller: Add SigmaStar SSD20xD gpi Daniel Palmer
2021-09-21 20:36   ` Rob Herring
2021-09-14 10:04 ` [PATCH 2/3] irqchip: " Daniel Palmer
2021-09-20  9:45   ` Marc Zyngier
2021-09-20 10:05     ` Daniel Palmer
2021-09-20 11:24       ` Marc Zyngier
2021-09-21  4:16         ` Daniel Palmer
2021-09-21  8:27           ` Marc Zyngier
2021-09-21 18:23             ` Linus Walleij
2021-09-30 12:39               ` Daniel Palmer
2021-09-30 13:07                 ` Marc Zyngier
2021-09-30 13:10                   ` Daniel Palmer
2021-09-30 13:06               ` Marc Zyngier [this message]
2021-09-30 13:36                 ` Daniel Palmer
2021-09-30 13:53                   ` Marc Zyngier
2021-09-30 13:59                     ` Daniel Palmer
2021-09-30 14:11                       ` Marc Zyngier
2021-09-30 16:10                         ` Linus Walleij
2021-09-30 16:13                   ` Linus Walleij
2021-10-01 12:33                     ` Daniel Palmer
2021-10-02  3:08                     ` Daniel Palmer
2021-09-21  6:11         ` Daniel Palmer
2021-09-14 10:04 ` [PATCH 3/3] ARM: dts: mstar: Add gpi interrupt controller to i2m Daniel Palmer
2021-09-14 15:59 ` [PATCH 0/3] SigmaStar SSD20XD GPIO interrupt controller Andrew Lunn
2021-09-15  9:06   ` Daniel Palmer
2021-09-15 20:34     ` Andrew Lunn
2021-09-20  8:36       ` Daniel Palmer

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