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([2a01:e0a:982:cbb0:b92a:81a9:df6e:1e3]) by smtp.gmail.com with ESMTPSA id 3-20020a05600c234300b003fc16ee2864sm13713955wmq.48.2023.08.01.02.42.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 01 Aug 2023 02:42:45 -0700 (PDT) Message-ID: <8753afee-e160-8252-9ab2-4b1dad82d432@linaro.org> Date: Tue, 1 Aug 2023 11:42:44 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 From: neil.armstrong@linaro.org Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH 6/9] drm/bridge: synopsys: dw-mipi-dsi: Set minimum lane byte clock cycles for HSA and HBP Content-Language: en-US To: Liu Ying , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: andrzej.hajda@intel.com, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com References: <20230717061831.1826878-1-victor.liu@nxp.com> <20230717061831.1826878-7-victor.liu@nxp.com> Organization: Linaro Developer Services In-Reply-To: <20230717061831.1826878-7-victor.liu@nxp.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 17/07/2023 08:18, Liu Ying wrote: > According to Synopsys support channel, each region of HSA, HBP and HFP must > have minimum number of 10 bytes where constant 4 bytes are for HSS or HSE > and 6 bytes are for blanking packet(header + CRC). Hence, the below table > comes in. > > +------------+----------+-------+ > | data lanes | min lbcc | bytes | > +------------+----------+-------+ > | 1 | 10 | 1*10 | > +------------+----------+-------+ > | 2 | 5 | 2*5 | > +------------+----------+-------+ > | 3 | 4 | 3*4 | > +------------+----------+-------+ > | 4 | 3 | 4*3 | > +------------+----------+-------+ > > Implement the minimum lbcc numbers to make sure that the values programmed > into DSI_VID_HSA_TIME and DSI_VID_HBP_TIME registers meet the minimum > number requirement. For DSI_VID_HLINE_TIME register, it seems that the > value programmed should be based on mode->htotal as-is, instead of sum up > HSA, HBP, HFP and HDISPLAY. > > This helps the case where Raydium RM67191 DSI panel is connected, since > it's video timing for hsync length is only 2 pixels and without this patch > the programmed value for DSI_VID_HSA_TIME is only 2 with 4 data lanes. > > Signed-off-by: Liu Ying > --- > drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c > index 332388fd86da..536306ccea5a 100644 > --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c > @@ -757,12 +757,19 @@ static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) > dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); > } > > +static const u32 minimum_lbccs[] = {10, 5, 4, 3}; > + > +static inline u32 dw_mipi_dsi_get_minimum_lbcc(struct dw_mipi_dsi *dsi) > +{ > + return minimum_lbccs[dsi->lanes - 1]; > +} > + > /* Get lane byte clock cycles. */ > static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, > const struct drm_display_mode *mode, > u32 hcomponent) > { > - u32 frac, lbcc; > + u32 frac, lbcc, minimum_lbcc; > int bpp; > > bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); > @@ -778,6 +785,11 @@ static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, > if (frac) > lbcc++; > > + minimum_lbcc = dw_mipi_dsi_get_minimum_lbcc(dsi); > + > + if (lbcc < minimum_lbcc) > + lbcc = minimum_lbcc; > + > return lbcc; > } > Reviewed-by: Neil Armstrong